]> git.droids-corp.org - dpdk.git/commitdiff
raw/cnxk_bphy: support changing CPRI misc settings
authorTomasz Duszynski <tduszynski@marvell.com>
Sat, 4 Jun 2022 16:26:48 +0000 (18:26 +0200)
committerThomas Monjalon <thomas@monjalon.net>
Wed, 22 Jun 2022 06:20:24 +0000 (08:20 +0200)
Add support for changing miscellaneous CPRI settings.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
doc/guides/rawdevs/cnxk_bphy.rst
drivers/common/cnxk/roc_bphy_cgx.c
drivers/common/cnxk/roc_bphy_cgx.h
drivers/common/cnxk/roc_bphy_cgx_priv.h
drivers/common/cnxk/version.map
drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
drivers/raw/cnxk_bphy/rte_pmd_bphy.h

index 50ee9bdaa6b26ca74ba10bb7964e232786202d28..2490912534f7ad8fc030a6f43645aafe3786c5ba 100644 (file)
@@ -121,6 +121,17 @@ Prior to sending actual message payload i.e
 ``struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl`` needs to be filled with relevant
 information.
 
+Change CPRI misc settings
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Message is used to change misc CPRI settings, for example to reset RX state
+machine on CPRI SERDES.
+
+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_MISC``.
+Prior to sending actual message payload i.e
+``struct cnxk_bphy_cgx_msg_cpri_mode_misc`` needs to be filled with relevant
+information.
+
 BPHY PMD
 --------
 
index ee0198924e547e588dfeddedf89ee8a013f1efda..4b6290516490d48cc0738643f1e2d1544c3bda23 100644 (file)
@@ -519,3 +519,33 @@ roc_bphy_cgx_cpri_mode_tx_control(struct roc_bphy_cgx *roc_cgx,
 
        return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
 }
+
+int
+roc_bphy_cgx_cpri_mode_misc(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+                           struct roc_bphy_cgx_cpri_mode_misc *mode)
+{
+       uint64_t scr1, scr0;
+
+       if (!(roc_model_is_cnf95xxn_a0() ||
+             roc_model_is_cnf95xxn_a1() ||
+             roc_model_is_cnf95xxn_b0()))
+               return -ENOTSUP;
+
+       if (!roc_cgx)
+               return -EINVAL;
+
+       if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+               return -ENODEV;
+
+       if (!mode)
+               return -EINVAL;
+
+       scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_CPRI_MISC) |
+              FIELD_PREP(SCR1_CPRI_MODE_MISC_ARGS_GSERC_IDX,
+                         mode->gserc_idx) |
+              FIELD_PREP(SCR1_CPRI_MODE_MISC_ARGS_LANE_IDX,
+                         mode->lane_idx) |
+              FIELD_PREP(SCR1_CPRI_MODE_MISC_ARGS_FLAGS, mode->flags);
+
+       return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+}
index b8023cce88464b21d712288bdf8f25745dd66629..3b645eb1300dcab95b8a9a25243b70129889abf1 100644 (file)
@@ -106,6 +106,12 @@ struct roc_bphy_cgx_cpri_mode_tx_ctrl {
        bool enable;
 };
 
+struct roc_bphy_cgx_cpri_mode_misc {
+       int gserc_idx;
+       int lane_idx;
+       int flags;
+};
+
 __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
 __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
 
@@ -138,5 +144,7 @@ __roc_api int roc_bphy_cgx_cpri_mode_change(struct roc_bphy_cgx *roc_cgx, unsign
                                            struct roc_bphy_cgx_cpri_mode_change *mode);
 __roc_api int roc_bphy_cgx_cpri_mode_tx_control(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
                                                struct roc_bphy_cgx_cpri_mode_tx_ctrl *mode);
+__roc_api int roc_bphy_cgx_cpri_mode_misc(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+                                         struct roc_bphy_cgx_cpri_mode_misc *mode);
 
 #endif /* _ROC_BPHY_CGX_H_ */
index 96db34f6a1222b89e00be34816d9b3319caa9b55..a1a4239cbe448d92713a02850e90b9f3928f7197 100644 (file)
@@ -71,6 +71,7 @@ enum eth_cmd_id {
        ETH_CMD_SET_PTP_MODE = 34,
        ETH_CMD_CPRI_MODE_CHANGE = 35,
        ETH_CMD_CPRI_TX_CONTROL = 36,
+       ETH_CMD_CPRI_MISC = 42,
 };
 
 /* event types - cause of interrupt */
@@ -147,6 +148,11 @@ enum eth_cmd_own {
 #define SCR1_CPRI_MODE_TX_CTRL_ARGS_LANE_IDX  GENMASK_ULL(15, 12)
 #define SCR1_CPRI_MODE_TX_CTRL_ARGS_ENABLE    BIT_ULL(16)
 
+/* struct cpri_mode_misc_args */
+#define SCR1_CPRI_MODE_MISC_ARGS_GSERC_IDX GENMASK_ULL(11, 8)
+#define SCR1_CPRI_MODE_MISC_ARGS_LANE_IDX  GENMASK_ULL(15, 12)
+#define SCR1_CPRI_MODE_MISC_ARGS_FLAGS     GENMASK_ULL(17, 16)
+
 #define SCR1_OWN_STATUS GENMASK_ULL(1, 0)
 
 #endif /* _ROC_BPHY_CGX_PRIV_H_ */
index a6183799a9c11f92a0ebb767cffb5d458e317fb1..d5fd1f41c25aaae38cd6f7f22b1eb7885b4c5d87 100644 (file)
@@ -29,6 +29,7 @@ INTERNAL {
        roc_ae_fpm_put;
        roc_aes_xcbc_key_derive;
        roc_bphy_cgx_cpri_mode_change;
+       roc_bphy_cgx_cpri_mode_misc;
        roc_bphy_cgx_cpri_mode_tx_control;
        roc_bphy_cgx_dev_fini;
        roc_bphy_cgx_dev_init;
index bdc65a7f2abb076405d566d92a2c12403b6ca2b9..de1c372334241036e7a8a3f586e6d7d89db37871 100644 (file)
@@ -59,10 +59,12 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue,
        struct cnxk_bphy_cgx_msg_cpri_mode_change *cpri_mode;
        struct cnxk_bphy_cgx_msg_set_link_state *link_state;
        struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl *tx_ctrl;
+       struct cnxk_bphy_cgx_msg_cpri_mode_misc *mode_misc;
        struct cnxk_bphy_cgx_msg *msg = buf->buf_addr;
        struct cnxk_bphy_cgx_msg_link_mode *link_mode;
        struct cnxk_bphy_cgx_msg_link_info *link_info;
        struct roc_bphy_cgx_cpri_mode_change rcpri_mode;
+       struct roc_bphy_cgx_cpri_mode_misc rmode_misc;
        struct roc_bphy_cgx_cpri_mode_tx_ctrl rtx_ctrl;
        struct roc_bphy_cgx_link_info rlink_info;
        struct roc_bphy_cgx_link_mode rlink_mode;
@@ -159,6 +161,14 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue,
                ret = roc_bphy_cgx_cpri_mode_tx_control(cgx->rcgx, lmac,
                                                        &rtx_ctrl);
                break;
+       case CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_MISC:
+               mode_misc = msg->data;
+               memset(&rmode_misc, 0, sizeof(rmode_misc));
+               rmode_misc.gserc_idx = mode_misc->gserc_idx;
+               rmode_misc.lane_idx = mode_misc->lane_idx;
+               rmode_misc.flags = mode_misc->flags;
+               ret = roc_bphy_cgx_cpri_mode_misc(cgx->rcgx, lmac, &rmode_misc);
+               break;
        default:
                return -EINVAL;
        }
index 79bb2233bce23445fd316802e86e550d8a6bbf10..86e58e4756a94c8e0f57ca9dbe5a7db7fcdbcacd 100644 (file)
@@ -54,6 +54,8 @@ enum cnxk_bphy_cgx_msg_type {
        CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_CHANGE,
        /** Type used to enable TX for CPRI SERDES */
        CNXK_BPHY_CGX_MSG_TYPE_CPRI_TX_CONTROL,
+       /** Type use to change misc CPRI SERDES settings */
+       CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_MISC,
 };
 
 /** Available link speeds */
@@ -197,6 +199,15 @@ struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl {
        bool enable;
 };
 
+struct cnxk_bphy_cgx_msg_cpri_mode_misc {
+       /** SERDES index (0 - 4) */
+       int gserc_idx;
+       /** Lane index (0 - 1) */
+       int lane_idx;
+       /** Misc flags (0 - RX Eq, 1 - RX state machine reset) */
+       int flags;
+};
+
 struct cnxk_bphy_cgx_msg {
        /** Message type */
        enum cnxk_bphy_cgx_msg_type type;
@@ -770,6 +781,31 @@ rte_pmd_bphy_cgx_cpri_tx_control(uint16_t dev_id, uint16_t lmac,
        return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
 }
 
+/**
+ * CPRI misc settings
+ *
+ * @param dev_id
+ *   The identifier of the device
+ * @param lmac
+ *   LMAC number for operation
+ * @param mode
+ *   CPRI settings holding misc control data
+ *
+ * @return
+ *   Returns 0 on success, negative error code otherwise
+ */
+static __rte_always_inline int
+rte_pmd_bphy_cgx_cpri_mode_misc(uint16_t dev_id, uint16_t lmac,
+                               struct cnxk_bphy_cgx_msg_cpri_mode_misc *mode)
+{
+       struct cnxk_bphy_cgx_msg msg = {
+               .type = CNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_MISC,
+               .data = mode,
+       };
+
+       return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
+}
+
 #ifdef __cplusplus
 }
 #endif