net/igb: fix Rx interrupt with VFIO and MSI-X
authorXiaoyun Li <xiaoyun.li@intel.com>
Mon, 6 Nov 2017 02:41:40 +0000 (10:41 +0800)
committerFerruh Yigit <ferruh.yigit@intel.com>
Tue, 7 Nov 2017 09:19:02 +0000 (10:19 +0100)
When using VFIO and MSIX interrupt mode, cannot get Rx interrupts. Because
when enabling the interrupt vectors, the offset is computed in a way which
only supports IGB_UIO. But the offset should be different when using VFIO.
This patch fixes this issue.

Fixes: c3cd3de0ab50 ("igb: enable Rx queue interrupts for PF")
Cc: stable@dpdk.org
Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
drivers/net/e1000/igb_ethdev.c

index 1877468..fdc139f 100644 (file)
@@ -5392,7 +5392,14 @@ eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
 {
        struct e1000_hw *hw =
                E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
-       uint32_t mask = 1 << queue_id;
+       struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
+       struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+       uint32_t vec = E1000_MISC_VEC_ID;
+
+       if (rte_intr_allow_others(intr_handle))
+               vec = E1000_RX_VEC_START;
+
+       uint32_t mask = 1 << (queue_id + vec);
 
        E1000_WRITE_REG(hw, E1000_EIMC, mask);
        E1000_WRITE_FLUSH(hw);
@@ -5407,7 +5414,12 @@ eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
                E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
        struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
        struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
-       uint32_t mask = 1 << queue_id;
+       uint32_t vec = E1000_MISC_VEC_ID;
+
+       if (rte_intr_allow_others(intr_handle))
+               vec = E1000_RX_VEC_START;
+
+       uint32_t mask = 1 << (queue_id + vec);
        uint32_t regval;
 
        regval = E1000_READ_REG(hw, E1000_EIMS);