STATIC void iavf_adminq_init_regs(struct iavf_hw *hw)
{
/* set head and tail registers in our local struct */
- if (iavf_is_vf(hw)) {
- hw->aq.asq.tail = IAVF_VF_ATQT1;
- hw->aq.asq.head = IAVF_VF_ATQH1;
- hw->aq.asq.len = IAVF_VF_ATQLEN1;
- hw->aq.asq.bal = IAVF_VF_ATQBAL1;
- hw->aq.asq.bah = IAVF_VF_ATQBAH1;
- hw->aq.arq.tail = IAVF_VF_ARQT1;
- hw->aq.arq.head = IAVF_VF_ARQH1;
- hw->aq.arq.len = IAVF_VF_ARQLEN1;
- hw->aq.arq.bal = IAVF_VF_ARQBAL1;
- hw->aq.arq.bah = IAVF_VF_ARQBAH1;
- }
+ hw->aq.asq.tail = IAVF_VF_ATQT1;
+ hw->aq.asq.head = IAVF_VF_ATQH1;
+ hw->aq.asq.len = IAVF_VF_ATQLEN1;
+ hw->aq.asq.bal = IAVF_VF_ATQBAL1;
+ hw->aq.asq.bah = IAVF_VF_ATQBAH1;
+ hw->aq.arq.tail = IAVF_VF_ARQT1;
+ hw->aq.arq.head = IAVF_VF_ARQH1;
+ hw->aq.arq.len = IAVF_VF_ARQLEN1;
+ hw->aq.arq.bal = IAVF_VF_ARQBAL1;
+ hw->aq.arq.bah = IAVF_VF_ARQBAH1;
}
/**
if (ret_code != IAVF_SUCCESS)
goto init_adminq_free_asq;
- ret_code = IAVF_SUCCESS;
-
/* success! */
goto init_adminq_exit;
iavf_destroy_spinlock(&hw->aq.asq_spinlock);
iavf_destroy_spinlock(&hw->aq.arq_spinlock);
- if (hw->nvm_buff.va)
- iavf_free_virt_mem(hw, &hw->nvm_buff);
-
return ret_code;
}
enum iavf_admin_queue_err arq_last_status;
};
-/**
- * iavf_aq_rc_to_posix - convert errors to user-land codes
- * aq_ret: AdminQ handler error code can override aq_rc
- * aq_rc: AdminQ firmware error code to convert
- **/
-STATIC INLINE int iavf_aq_rc_to_posix(int aq_ret, int aq_rc)
-{
- int aq_to_posix[] = {
- 0, /* IAVF_AQ_RC_OK */
- -EPERM, /* IAVF_AQ_RC_EPERM */
- -ENOENT, /* IAVF_AQ_RC_ENOENT */
- -ESRCH, /* IAVF_AQ_RC_ESRCH */
- -EINTR, /* IAVF_AQ_RC_EINTR */
- -EIO, /* IAVF_AQ_RC_EIO */
- -ENXIO, /* IAVF_AQ_RC_ENXIO */
- -E2BIG, /* IAVF_AQ_RC_E2BIG */
- -EAGAIN, /* IAVF_AQ_RC_EAGAIN */
- -ENOMEM, /* IAVF_AQ_RC_ENOMEM */
- -EACCES, /* IAVF_AQ_RC_EACCES */
- -EFAULT, /* IAVF_AQ_RC_EFAULT */
- -EBUSY, /* IAVF_AQ_RC_EBUSY */
- -EEXIST, /* IAVF_AQ_RC_EEXIST */
- -EINVAL, /* IAVF_AQ_RC_EINVAL */
- -ENOTTY, /* IAVF_AQ_RC_ENOTTY */
- -ENOSPC, /* IAVF_AQ_RC_ENOSPC */
- -ENOSYS, /* IAVF_AQ_RC_ENOSYS */
- -ERANGE, /* IAVF_AQ_RC_ERANGE */
- -EPIPE, /* IAVF_AQ_RC_EFLUSHED */
- -ESPIPE, /* IAVF_AQ_RC_BAD_ADDR */
- -EROFS, /* IAVF_AQ_RC_EMODE */
- -EFBIG, /* IAVF_AQ_RC_EFBIG */
- };
-
- /* aq_rc is invalid if AQ timed out */
- if (aq_ret == IAVF_ERR_ADMIN_QUEUE_TIMEOUT)
- return -EAGAIN;
-
- if (!((u32)aq_rc < (sizeof(aq_to_posix) / sizeof((aq_to_posix)[0]))))
- return -ERANGE;
-
- return aq_to_posix[aq_rc];
-}
-
/* general information */
#define IAVF_AQ_LARGE_BUF 512
#define IAVF_ASQ_CMD_TIMEOUT 250000 /* usecs */
* This file needs to comply with the Linux Kernel coding style.
*/
-
#define IAVF_FW_API_VERSION_MAJOR 0x0001
#define IAVF_FW_API_VERSION_MINOR_X722 0x0005
#define IAVF_FW_API_VERSION_MINOR_X710 0x0007
*/
#define IAVF_CHECK_CMD_LENGTH(X) IAVF_CHECK_STRUCT_LEN(16, X)
-/* internal (0x00XX) commands */
-
-/* Get version (direct 0x0001) */
-struct iavf_aqc_get_version {
- __le32 rom_ver;
- __le32 fw_build;
- __le16 fw_major;
- __le16 fw_minor;
- __le16 api_major;
- __le16 api_minor;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_version);
-
-/* Send driver version (indirect 0x0002) */
-struct iavf_aqc_driver_version {
- u8 driver_major_ver;
- u8 driver_minor_ver;
- u8 driver_build_ver;
- u8 driver_subbuild_ver;
- u8 reserved[4];
- __le32 address_high;
- __le32 address_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_driver_version);
-
/* Queue Shutdown (direct 0x0003) */
struct iavf_aqc_queue_shutdown {
__le32 driver_unloading;
IAVF_CHECK_CMD_LENGTH(iavf_aqc_queue_shutdown);
-/* Set PF context (0x0004, direct) */
-struct iavf_aqc_set_pf_context {
- u8 pf_id;
- u8 reserved[15];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_pf_context);
-
-/* Request resource ownership (direct 0x0008)
- * Release resource ownership (direct 0x0009)
- */
-#define IAVF_AQ_RESOURCE_NVM 1
-#define IAVF_AQ_RESOURCE_SDP 2
-#define IAVF_AQ_RESOURCE_ACCESS_READ 1
-#define IAVF_AQ_RESOURCE_ACCESS_WRITE 2
-#define IAVF_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
-#define IAVF_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
-
-struct iavf_aqc_request_resource {
- __le16 resource_id;
- __le16 access_type;
- __le32 timeout;
- __le32 resource_number;
- u8 reserved[4];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_request_resource);
-
-/* Get function capabilities (indirect 0x000A)
- * Get device capabilities (indirect 0x000B)
- */
-struct iavf_aqc_list_capabilites {
- u8 command_flags;
-#define IAVF_AQ_LIST_CAP_PF_INDEX_EN 1
- u8 pf_index;
- u8 reserved[2];
- __le32 count;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_list_capabilites);
-
-struct iavf_aqc_list_capabilities_element_resp {
- __le16 id;
- u8 major_rev;
- u8 minor_rev;
- __le32 number;
- __le32 logical_id;
- __le32 phys_id;
- u8 reserved[16];
-};
-
-/* list of caps */
-
-#define IAVF_AQ_CAP_ID_SWITCH_MODE 0x0001
-#define IAVF_AQ_CAP_ID_MNG_MODE 0x0002
-#define IAVF_AQ_CAP_ID_NPAR_ACTIVE 0x0003
-#define IAVF_AQ_CAP_ID_OS2BMC_CAP 0x0004
-#define IAVF_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
-#define IAVF_AQ_CAP_ID_ALTERNATE_RAM 0x0006
-#define IAVF_AQ_CAP_ID_WOL_AND_PROXY 0x0008
-#define IAVF_AQ_CAP_ID_SRIOV 0x0012
-#define IAVF_AQ_CAP_ID_VF 0x0013
-#define IAVF_AQ_CAP_ID_VMDQ 0x0014
-#define IAVF_AQ_CAP_ID_8021QBG 0x0015
-#define IAVF_AQ_CAP_ID_8021QBR 0x0016
-#define IAVF_AQ_CAP_ID_VSI 0x0017
-#define IAVF_AQ_CAP_ID_DCB 0x0018
-#define IAVF_AQ_CAP_ID_FCOE 0x0021
-#define IAVF_AQ_CAP_ID_ISCSI 0x0022
-#define IAVF_AQ_CAP_ID_RSS 0x0040
-#define IAVF_AQ_CAP_ID_RXQ 0x0041
-#define IAVF_AQ_CAP_ID_TXQ 0x0042
-#define IAVF_AQ_CAP_ID_MSIX 0x0043
-#define IAVF_AQ_CAP_ID_VF_MSIX 0x0044
-#define IAVF_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
-#define IAVF_AQ_CAP_ID_1588 0x0046
-#define IAVF_AQ_CAP_ID_IWARP 0x0051
-#define IAVF_AQ_CAP_ID_LED 0x0061
-#define IAVF_AQ_CAP_ID_SDP 0x0062
-#define IAVF_AQ_CAP_ID_MDIO 0x0063
-#define IAVF_AQ_CAP_ID_WSR_PROT 0x0064
-#define IAVF_AQ_CAP_ID_NVM_MGMT 0x0080
-#define IAVF_AQ_CAP_ID_FLEX10 0x00F1
-#define IAVF_AQ_CAP_ID_CEM 0x00F2
-
-/* Set CPPM Configuration (direct 0x0103) */
-struct iavf_aqc_cppm_configuration {
- __le16 command_flags;
-#define IAVF_AQ_CPPM_EN_LTRC 0x0800
-#define IAVF_AQ_CPPM_EN_DMCTH 0x1000
-#define IAVF_AQ_CPPM_EN_DMCTLX 0x2000
-#define IAVF_AQ_CPPM_EN_HPTC 0x4000
-#define IAVF_AQ_CPPM_EN_DMARC 0x8000
- __le16 ttlx;
- __le32 dmacr;
- __le16 dmcth;
- u8 hptc;
- u8 reserved;
- __le32 pfltrc;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_cppm_configuration);
-
-/* Set ARP Proxy command / response (indirect 0x0104) */
-struct iavf_aqc_arp_proxy_data {
- __le16 command_flags;
-#define IAVF_AQ_ARP_INIT_IPV4 0x0800
-#define IAVF_AQ_ARP_UNSUP_CTL 0x1000
-#define IAVF_AQ_ARP_ENA 0x2000
-#define IAVF_AQ_ARP_ADD_IPV4 0x4000
-#define IAVF_AQ_ARP_DEL_IPV4 0x8000
- __le16 table_id;
- __le32 enabled_offloads;
-#define IAVF_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020
-#define IAVF_AQ_ARP_OFFLOAD_ENABLE 0x00000800
- __le32 ip_addr;
- u8 mac_addr[6];
- u8 reserved[2];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x14, iavf_aqc_arp_proxy_data);
-
-/* Set NS Proxy Table Entry Command (indirect 0x0105) */
-struct iavf_aqc_ns_proxy_data {
- __le16 table_idx_mac_addr_0;
- __le16 table_idx_mac_addr_1;
- __le16 table_idx_ipv6_0;
- __le16 table_idx_ipv6_1;
- __le16 control;
-#define IAVF_AQ_NS_PROXY_ADD_0 0x0001
-#define IAVF_AQ_NS_PROXY_DEL_0 0x0002
-#define IAVF_AQ_NS_PROXY_ADD_1 0x0004
-#define IAVF_AQ_NS_PROXY_DEL_1 0x0008
-#define IAVF_AQ_NS_PROXY_ADD_IPV6_0 0x0010
-#define IAVF_AQ_NS_PROXY_DEL_IPV6_0 0x0020
-#define IAVF_AQ_NS_PROXY_ADD_IPV6_1 0x0040
-#define IAVF_AQ_NS_PROXY_DEL_IPV6_1 0x0080
-#define IAVF_AQ_NS_PROXY_COMMAND_SEQ 0x0100
-#define IAVF_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200
-#define IAVF_AQ_NS_PROXY_INIT_MAC_TBL 0x0400
-#define IAVF_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
-#define IAVF_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000
- u8 mac_addr_0[6];
- u8 mac_addr_1[6];
- u8 local_mac_addr[6];
- u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
- u8 ipv6_addr_1[16];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x3c, iavf_aqc_ns_proxy_data);
-
-/* Manage LAA Command (0x0106) - obsolete */
-struct iavf_aqc_mng_laa {
- __le16 command_flags;
-#define IAVF_AQ_LAA_FLAG_WR 0x8000
- u8 reserved[2];
- __le32 sal;
- __le16 sah;
- u8 reserved2[6];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_mng_laa);
-
-/* Manage MAC Address Read Command (indirect 0x0107) */
-struct iavf_aqc_mac_address_read {
- __le16 command_flags;
-#define IAVF_AQC_LAN_ADDR_VALID 0x10
-#define IAVF_AQC_SAN_ADDR_VALID 0x20
-#define IAVF_AQC_PORT_ADDR_VALID 0x40
-#define IAVF_AQC_WOL_ADDR_VALID 0x80
-#define IAVF_AQC_MC_MAG_EN_VALID 0x100
#define IAVF_AQC_WOL_PRESERVE_STATUS 0x200
-#define IAVF_AQC_ADDR_VALID_MASK 0x3F0
- u8 reserved[6];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_mac_address_read);
-
-struct iavf_aqc_mac_address_read_data {
- u8 pf_lan_mac[6];
- u8 pf_san_mac[6];
- u8 port_mac[6];
- u8 pf_wol_mac[6];
-};
-
-IAVF_CHECK_STRUCT_LEN(24, iavf_aqc_mac_address_read_data);
-
-/* Manage MAC Address Write Command (0x0108) */
-struct iavf_aqc_mac_address_write {
- __le16 command_flags;
#define IAVF_AQC_MC_MAG_EN 0x0100
#define IAVF_AQC_WOL_PRESERVE_ON_PFR 0x0200
-#define IAVF_AQC_WRITE_TYPE_LAA_ONLY 0x0000
-#define IAVF_AQC_WRITE_TYPE_LAA_WOL 0x4000
-#define IAVF_AQC_WRITE_TYPE_PORT 0x8000
-#define IAVF_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
-#define IAVF_AQC_WRITE_TYPE_MASK 0xC000
-
- __le16 mac_sah;
- __le32 mac_sal;
- u8 reserved[8];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_mac_address_write);
-
-/* PXE commands (0x011x) */
-
-/* Clear PXE Command and response (direct 0x0110) */
-struct iavf_aqc_clear_pxe {
- u8 rx_cnt;
- u8 reserved[15];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_clear_pxe);
-
-/* Set WoL Filter (0x0120) */
-
-struct iavf_aqc_set_wol_filter {
- __le16 filter_index;
-#define IAVF_AQC_MAX_NUM_WOL_FILTERS 8
-#define IAVF_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15
-#define IAVF_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
- IAVF_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
-
-#define IAVF_AQC_SET_WOL_FILTER_INDEX_SHIFT 0
-#define IAVF_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \
- IAVF_AQC_SET_WOL_FILTER_INDEX_SHIFT)
- __le16 cmd_flags;
-#define IAVF_AQC_SET_WOL_FILTER 0x8000
-#define IAVF_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
-#define IAVF_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000
-#define IAVF_AQC_SET_WOL_FILTER_ACTION_CLEAR 0
-#define IAVF_AQC_SET_WOL_FILTER_ACTION_SET 1
- __le16 valid_flags;
-#define IAVF_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
-#define IAVF_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
- u8 reserved[2];
- __le32 address_high;
- __le32 address_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_wol_filter);
-
-struct iavf_aqc_set_wol_filter_data {
- u8 filter[128];
- u8 mask[16];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x90, iavf_aqc_set_wol_filter_data);
-
-/* Get Wake Reason (0x0121) */
-
-struct iavf_aqc_get_wake_reason_completion {
- u8 reserved_1[2];
- __le16 wake_reason;
-#define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0
-#define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
- IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
-#define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8
-#define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \
- IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
- u8 reserved_2[12];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_wake_reason_completion);
-
-/* Switch configuration commands (0x02xx) */
-
-/* Used by many indirect commands that only pass an seid and a buffer in the
- * command
- */
-struct iavf_aqc_switch_seid {
- __le16 seid;
- u8 reserved[6];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_switch_seid);
-
-/* Get Switch Configuration command (indirect 0x0200)
- * uses iavf_aqc_switch_seid for the descriptor
- */
-struct iavf_aqc_get_switch_config_header_resp {
- __le16 num_reported;
- __le16 num_total;
- u8 reserved[12];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_switch_config_header_resp);
-
-struct iavf_aqc_switch_config_element_resp {
- u8 element_type;
-#define IAVF_AQ_SW_ELEM_TYPE_MAC 1
-#define IAVF_AQ_SW_ELEM_TYPE_PF 2
-#define IAVF_AQ_SW_ELEM_TYPE_VF 3
-#define IAVF_AQ_SW_ELEM_TYPE_EMP 4
-#define IAVF_AQ_SW_ELEM_TYPE_BMC 5
-#define IAVF_AQ_SW_ELEM_TYPE_PV 16
-#define IAVF_AQ_SW_ELEM_TYPE_VEB 17
-#define IAVF_AQ_SW_ELEM_TYPE_PA 18
-#define IAVF_AQ_SW_ELEM_TYPE_VSI 19
- u8 revision;
-#define IAVF_AQ_SW_ELEM_REV_1 1
- __le16 seid;
- __le16 uplink_seid;
- __le16 downlink_seid;
- u8 reserved[3];
- u8 connection_type;
-#define IAVF_AQ_CONN_TYPE_REGULAR 0x1
-#define IAVF_AQ_CONN_TYPE_DEFAULT 0x2
-#define IAVF_AQ_CONN_TYPE_CASCADED 0x3
- __le16 scheduler_id;
- __le16 element_info;
-};
-
-IAVF_CHECK_STRUCT_LEN(0x10, iavf_aqc_switch_config_element_resp);
-
-/* Get Switch Configuration (indirect 0x0200)
- * an array of elements are returned in the response buffer
- * the first in the array is the header, remainder are elements
- */
-struct iavf_aqc_get_switch_config_resp {
- struct iavf_aqc_get_switch_config_header_resp header;
- struct iavf_aqc_switch_config_element_resp element[1];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_get_switch_config_resp);
-
-/* Add Statistics (direct 0x0201)
- * Remove Statistics (direct 0x0202)
- */
-struct iavf_aqc_add_remove_statistics {
- __le16 seid;
- __le16 vlan;
- __le16 stat_index;
- u8 reserved[10];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_statistics);
-
-/* Set Port Parameters command (direct 0x0203) */
-struct iavf_aqc_set_port_parameters {
- __le16 command_flags;
-#define IAVF_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
-#define IAVF_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
-#define IAVF_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
- __le16 bad_frame_vsi;
-#define IAVF_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0
-#define IAVF_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF
- __le16 default_seid; /* reserved for command */
- u8 reserved[10];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_port_parameters);
-
-/* Get Switch Resource Allocation (indirect 0x0204) */
-struct iavf_aqc_get_switch_resource_alloc {
- u8 num_entries; /* reserved for command */
- u8 reserved[7];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_switch_resource_alloc);
-
-/* expect an array of these structs in the response buffer */
-struct iavf_aqc_switch_resource_alloc_element_resp {
- u8 resource_type;
-#define IAVF_AQ_RESOURCE_TYPE_VEB 0x0
-#define IAVF_AQ_RESOURCE_TYPE_VSI 0x1
-#define IAVF_AQ_RESOURCE_TYPE_MACADDR 0x2
-#define IAVF_AQ_RESOURCE_TYPE_STAG 0x3
-#define IAVF_AQ_RESOURCE_TYPE_ETAG 0x4
-#define IAVF_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
-#define IAVF_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
-#define IAVF_AQ_RESOURCE_TYPE_VLAN 0x7
-#define IAVF_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
-#define IAVF_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
-#define IAVF_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
-#define IAVF_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
-#define IAVF_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
-#define IAVF_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
-#define IAVF_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
-#define IAVF_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
-#define IAVF_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
-#define IAVF_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
-#define IAVF_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
- u8 reserved1;
- __le16 guaranteed;
- __le16 total;
- __le16 used;
- __le16 total_unalloced;
- u8 reserved2[6];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x10, iavf_aqc_switch_resource_alloc_element_resp);
-
-/* Set Switch Configuration (direct 0x0205) */
-struct iavf_aqc_set_switch_config {
- __le16 flags;
-/* flags used for both fields below */
-#define IAVF_AQ_SET_SWITCH_CFG_PROMISC 0x0001
-#define IAVF_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
-#define IAVF_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004
- __le16 valid_flags;
- /* The ethertype in switch_tag is dropped on ingress and used
- * internally by the switch. Set this to zero for the default
- * of 0x88a8 (802.1ad). Should be zero for firmware API
- * versions lower than 1.7.
- */
- __le16 switch_tag;
- /* The ethertypes in first_tag and second_tag are used to
- * match the outer and inner VLAN tags (respectively) when HW
- * double VLAN tagging is enabled via the set port parameters
- * AQ command. Otherwise these are both ignored. Set them to
- * zero for their defaults of 0x8100 (802.1Q). Should be zero
- * for firmware API versions lower than 1.7.
- */
- __le16 first_tag;
- __le16 second_tag;
- u8 reserved[6];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_switch_config);
-
-/* Read Receive control registers (direct 0x0206)
- * Write Receive control registers (direct 0x0207)
- * used for accessing Rx control registers that can be
- * slow and need special handling when under high Rx load
- */
-struct iavf_aqc_rx_ctl_reg_read_write {
- __le32 reserved1;
- __le32 address;
- __le32 reserved2;
- __le32 value;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_rx_ctl_reg_read_write);
-
-/* Add VSI (indirect 0x0210)
- * this indirect command uses struct iavf_aqc_vsi_properties_data
- * as the indirect buffer (128 bytes)
- *
- * Update VSI (indirect 0x211)
- * uses the same data structure as Add VSI
- *
- * Get VSI (indirect 0x0212)
- * uses the same completion and data structure as Add VSI
- */
-struct iavf_aqc_add_get_update_vsi {
- __le16 uplink_seid;
- u8 connection_type;
-#define IAVF_AQ_VSI_CONN_TYPE_NORMAL 0x1
-#define IAVF_AQ_VSI_CONN_TYPE_DEFAULT 0x2
-#define IAVF_AQ_VSI_CONN_TYPE_CASCADED 0x3
- u8 reserved1;
- u8 vf_id;
- u8 reserved2;
- __le16 vsi_flags;
-#define IAVF_AQ_VSI_TYPE_SHIFT 0x0
-#define IAVF_AQ_VSI_TYPE_MASK (0x3 << IAVF_AQ_VSI_TYPE_SHIFT)
-#define IAVF_AQ_VSI_TYPE_VF 0x0
-#define IAVF_AQ_VSI_TYPE_VMDQ2 0x1
-#define IAVF_AQ_VSI_TYPE_PF 0x2
-#define IAVF_AQ_VSI_TYPE_EMP_MNG 0x3
-#define IAVF_AQ_VSI_FLAG_CASCADED_PV 0x4
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_get_update_vsi);
-
-struct iavf_aqc_add_get_update_vsi_completion {
- __le16 seid;
- __le16 vsi_number;
- __le16 vsi_used;
- __le16 vsi_free;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_get_update_vsi_completion);
struct iavf_aqc_vsi_properties_data {
/* first 96 byte are written by SW */
IAVF_CHECK_STRUCT_LEN(128, iavf_aqc_vsi_properties_data);
-/* Add Port Virtualizer (direct 0x0220)
- * also used for update PV (direct 0x0221) but only flags are used
- * (IS_CTRL_PORT only works on add PV)
- */
-struct iavf_aqc_add_update_pv {
- __le16 command_flags;
-#define IAVF_AQC_PV_FLAG_PV_TYPE 0x1
-#define IAVF_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
-#define IAVF_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
-#define IAVF_AQC_PV_FLAG_IS_CTRL_PORT 0x8
- __le16 uplink_seid;
- __le16 connected_seid;
- u8 reserved[10];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_update_pv);
-
-struct iavf_aqc_add_update_pv_completion {
- /* reserved for update; for add also encodes error if rc == ENOSPC */
- __le16 pv_seid;
-#define IAVF_AQC_PV_ERR_FLAG_NO_PV 0x1
-#define IAVF_AQC_PV_ERR_FLAG_NO_SCHED 0x2
-#define IAVF_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
-#define IAVF_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
- u8 reserved[14];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_update_pv_completion);
-
-/* Get PV Params (direct 0x0222)
- * uses iavf_aqc_switch_seid for the descriptor
- */
-
-struct iavf_aqc_get_pv_params_completion {
- __le16 seid;
- __le16 default_stag;
- __le16 pv_flags; /* same flags as add_pv */
-#define IAVF_AQC_GET_PV_PV_TYPE 0x1
-#define IAVF_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
-#define IAVF_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
- u8 reserved[8];
- __le16 default_port_seid;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_pv_params_completion);
-
-/* Add VEB (direct 0x0230) */
-struct iavf_aqc_add_veb {
- __le16 uplink_seid;
- __le16 downlink_seid;
- __le16 veb_flags;
-#define IAVF_AQC_ADD_VEB_FLOATING 0x1
-#define IAVF_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
-#define IAVF_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
- IAVF_AQC_ADD_VEB_PORT_TYPE_SHIFT)
-#define IAVF_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
-#define IAVF_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
-#define IAVF_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
-#define IAVF_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
- u8 enable_tcs;
- u8 reserved[9];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_veb);
-
-struct iavf_aqc_add_veb_completion {
- u8 reserved[6];
- __le16 switch_seid;
- /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
- __le16 veb_seid;
-#define IAVF_AQC_VEB_ERR_FLAG_NO_VEB 0x1
-#define IAVF_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
-#define IAVF_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
-#define IAVF_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
- __le16 statistic_index;
- __le16 vebs_used;
- __le16 vebs_free;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_veb_completion);
-
/* Get VEB Parameters (direct 0x0232)
* uses iavf_aqc_switch_seid for the descriptor
*/
IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_veb_parameters_completion);
-/* Delete Element (direct 0x0243)
- * uses the generic iavf_aqc_switch_seid
- */
-
-/* Add MAC-VLAN (indirect 0x0250) */
-
-/* used for the command for most vlan commands */
-struct iavf_aqc_macvlan {
- __le16 num_addresses;
- __le16 seid[3];
-#define IAVF_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
-#define IAVF_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
- IAVF_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
-#define IAVF_AQC_MACVLAN_CMD_SEID_VALID 0x8000
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_macvlan);
-
-/* indirect data for command and response */
-struct iavf_aqc_add_macvlan_element_data {
- u8 mac_addr[6];
- __le16 vlan_tag;
- __le16 flags;
-#define IAVF_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
-#define IAVF_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
-#define IAVF_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
-#define IAVF_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
-#define IAVF_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
- __le16 queue_number;
-#define IAVF_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
-#define IAVF_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
- IAVF_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
- /* response section */
- u8 match_method;
-#define IAVF_AQC_MM_PERFECT_MATCH 0x01
-#define IAVF_AQC_MM_HASH_MATCH 0x02
-#define IAVF_AQC_MM_ERR_NO_RES 0xFF
- u8 reserved1[3];
-};
+#define IAVF_LINK_SPEED_100MB_SHIFT 0x1
+#define IAVF_LINK_SPEED_1000MB_SHIFT 0x2
+#define IAVF_LINK_SPEED_10GB_SHIFT 0x3
+#define IAVF_LINK_SPEED_40GB_SHIFT 0x4
+#define IAVF_LINK_SPEED_20GB_SHIFT 0x5
+#define IAVF_LINK_SPEED_25GB_SHIFT 0x6
-struct iavf_aqc_add_remove_macvlan_completion {
- __le16 perfect_mac_used;
- __le16 perfect_mac_free;
- __le16 unicast_hash_free;
- __le16 multicast_hash_free;
- __le32 addr_high;
- __le32 addr_low;
+enum iavf_aq_link_speed {
+ IAVF_LINK_SPEED_UNKNOWN = 0,
+ IAVF_LINK_SPEED_100MB = (1 << IAVF_LINK_SPEED_100MB_SHIFT),
+ IAVF_LINK_SPEED_1GB = (1 << IAVF_LINK_SPEED_1000MB_SHIFT),
+ IAVF_LINK_SPEED_10GB = (1 << IAVF_LINK_SPEED_10GB_SHIFT),
+ IAVF_LINK_SPEED_40GB = (1 << IAVF_LINK_SPEED_40GB_SHIFT),
+ IAVF_LINK_SPEED_20GB = (1 << IAVF_LINK_SPEED_20GB_SHIFT),
+ IAVF_LINK_SPEED_25GB = (1 << IAVF_LINK_SPEED_25GB_SHIFT),
};
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_macvlan_completion);
-
-/* Remove MAC-VLAN (indirect 0x0251)
- * uses iavf_aqc_macvlan for the descriptor
- * data points to an array of num_addresses of elements
- */
-
-struct iavf_aqc_remove_macvlan_element_data {
- u8 mac_addr[6];
- __le16 vlan_tag;
- u8 flags;
-#define IAVF_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
-#define IAVF_AQC_MACVLAN_DEL_HASH_MATCH 0x02
-#define IAVF_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
-#define IAVF_AQC_MACVLAN_DEL_ALL_VSIS 0x10
- u8 reserved[3];
- /* reply section */
- u8 error_code;
-#define IAVF_AQC_REMOVE_MACVLAN_SUCCESS 0x0
-#define IAVF_AQC_REMOVE_MACVLAN_FAIL 0xFF
- u8 reply_reserved[3];
-};
+#define IAVF_AQ_LINK_UP_FUNCTION 0x01
-/* Add VLAN (indirect 0x0252)
- * Remove VLAN (indirect 0x0253)
- * use the generic iavf_aqc_macvlan for the command
+/* Send to PF command (indirect 0x0801) id is only used by PF
+ * Send to VF command (indirect 0x0802) id is only used by PF
+ * Send to Peer PF command (indirect 0x0803)
*/
-struct iavf_aqc_add_remove_vlan_element_data {
- __le16 vlan_tag;
- u8 vlan_flags;
-/* flags for add VLAN */
-#define IAVF_AQC_ADD_VLAN_LOCAL 0x1
-#define IAVF_AQC_ADD_PVLAN_TYPE_SHIFT 1
-#define IAVF_AQC_ADD_PVLAN_TYPE_MASK (0x3 << IAVF_AQC_ADD_PVLAN_TYPE_SHIFT)
-#define IAVF_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
-#define IAVF_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
-#define IAVF_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
-#define IAVF_AQC_VLAN_PTYPE_SHIFT 3
-#define IAVF_AQC_VLAN_PTYPE_MASK (0x3 << IAVF_AQC_VLAN_PTYPE_SHIFT)
-#define IAVF_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
-#define IAVF_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
-#define IAVF_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
-#define IAVF_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
-/* flags for remove VLAN */
-#define IAVF_AQC_REMOVE_VLAN_ALL 0x1
- u8 reserved;
- u8 result;
-/* flags for add VLAN */
-#define IAVF_AQC_ADD_VLAN_SUCCESS 0x0
-#define IAVF_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
-#define IAVF_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
-/* flags for remove VLAN */
-#define IAVF_AQC_REMOVE_VLAN_SUCCESS 0x0
-#define IAVF_AQC_REMOVE_VLAN_FAIL 0xFF
- u8 reserved1[3];
-};
-
-struct iavf_aqc_add_remove_vlan_completion {
+struct iavf_aqc_pf_vf_message {
+ __le32 id;
u8 reserved[4];
- __le16 vlans_used;
- __le16 vlans_free;
__le32 addr_high;
__le32 addr_low;
};
-/* Set VSI Promiscuous Modes (direct 0x0254) */
-struct iavf_aqc_set_vsi_promiscuous_modes {
- __le16 promiscuous_flags;
- __le16 valid_flags;
-/* flags used for both fields above */
-#define IAVF_AQC_SET_VSI_PROMISC_UNICAST 0x01
-#define IAVF_AQC_SET_VSI_PROMISC_MULTICAST 0x02
-#define IAVF_AQC_SET_VSI_PROMISC_BROADCAST 0x04
-#define IAVF_AQC_SET_VSI_DEFAULT 0x08
-#define IAVF_AQC_SET_VSI_PROMISC_VLAN 0x10
-#define IAVF_AQC_SET_VSI_PROMISC_TX 0x8000
- __le16 seid;
-#define IAVF_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
- __le16 vlan_tag;
-#define IAVF_AQC_SET_VSI_VLAN_MASK 0x0FFF
-#define IAVF_AQC_SET_VSI_VLAN_VALID 0x8000
- u8 reserved[8];
-};
+IAVF_CHECK_CMD_LENGTH(iavf_aqc_pf_vf_message);
+
+/* Get CEE DCBX Oper Config (0x0A07)
+ * uses the generic descriptor struct
+ * returns below as indirect response
+ */
+
+#define IAVF_AQC_CEE_APP_FCOE_SHIFT 0x0
+#define IAVF_AQC_CEE_APP_FCOE_MASK (0x7 << IAVF_AQC_CEE_APP_FCOE_SHIFT)
+#define IAVF_AQC_CEE_APP_ISCSI_SHIFT 0x3
+#define IAVF_AQC_CEE_APP_ISCSI_MASK (0x7 << IAVF_AQC_CEE_APP_ISCSI_SHIFT)
+#define IAVF_AQC_CEE_APP_FIP_SHIFT 0x8
+#define IAVF_AQC_CEE_APP_FIP_MASK (0x7 << IAVF_AQC_CEE_APP_FIP_SHIFT)
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_vsi_promiscuous_modes);
+#define IAVF_AQC_CEE_PG_STATUS_SHIFT 0x0
+#define IAVF_AQC_CEE_PG_STATUS_MASK (0x7 << IAVF_AQC_CEE_PG_STATUS_SHIFT)
+#define IAVF_AQC_CEE_PFC_STATUS_SHIFT 0x3
+#define IAVF_AQC_CEE_PFC_STATUS_MASK (0x7 << IAVF_AQC_CEE_PFC_STATUS_SHIFT)
+#define IAVF_AQC_CEE_APP_STATUS_SHIFT 0x8
+#define IAVF_AQC_CEE_APP_STATUS_MASK (0x7 << IAVF_AQC_CEE_APP_STATUS_SHIFT)
+#define IAVF_AQC_CEE_FCOE_STATUS_SHIFT 0x8
+#define IAVF_AQC_CEE_FCOE_STATUS_MASK (0x7 << IAVF_AQC_CEE_FCOE_STATUS_SHIFT)
+#define IAVF_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
+#define IAVF_AQC_CEE_ISCSI_STATUS_MASK (0x7 << IAVF_AQC_CEE_ISCSI_STATUS_SHIFT)
+#define IAVF_AQC_CEE_FIP_STATUS_SHIFT 0x10
+#define IAVF_AQC_CEE_FIP_STATUS_MASK (0x7 << IAVF_AQC_CEE_FIP_STATUS_SHIFT)
-/* Add S/E-tag command (direct 0x0255)
- * Uses generic iavf_aqc_add_remove_tag_completion for completion
+/* struct iavf_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
+ * word boundary layout issues, which the Linux compilers silently deal
+ * with by adding padding, making the actual struct larger than designed.
+ * However, the FW compiler for the NIC is less lenient and complains
+ * about the struct. Hence, the struct defined here has an extra byte in
+ * fields reserved3 and reserved4 to directly acknowledge that padding,
+ * and the new length is used in the length check macro.
*/
-struct iavf_aqc_add_tag {
- __le16 flags;
-#define IAVF_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
- __le16 seid;
-#define IAVF_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
-#define IAVF_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
- IAVF_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
- __le16 tag;
- __le16 queue_number;
- u8 reserved[8];
+struct iavf_aqc_get_cee_dcb_cfg_v1_resp {
+ u8 reserved1;
+ u8 oper_num_tc;
+ u8 oper_prio_tc[4];
+ u8 reserved2;
+ u8 oper_tc_bw[8];
+ u8 oper_pfc_en;
+ u8 reserved3[2];
+ __le16 oper_app_prio;
+ u8 reserved4[2];
+ __le16 tlv_status;
};
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_tag);
+IAVF_CHECK_STRUCT_LEN(0x18, iavf_aqc_get_cee_dcb_cfg_v1_resp);
-struct iavf_aqc_add_remove_tag_completion {
+struct iavf_aqc_get_cee_dcb_cfg_resp {
+ u8 oper_num_tc;
+ u8 oper_prio_tc[4];
+ u8 oper_tc_bw[8];
+ u8 oper_pfc_en;
+ __le16 oper_app_prio;
+ __le32 tlv_status;
u8 reserved[12];
- __le16 tags_used;
- __le16 tags_free;
};
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_tag_completion);
+IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_get_cee_dcb_cfg_resp);
-/* Remove S/E-tag command (direct 0x0256)
- * Uses generic iavf_aqc_add_remove_tag_completion for completion
+/* Set Local LLDP MIB (indirect 0x0A08)
+ * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
*/
-struct iavf_aqc_remove_tag {
- __le16 seid;
-#define IAVF_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
-#define IAVF_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
- IAVF_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
- __le16 tag;
- u8 reserved[12];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_remove_tag);
-
-/* Add multicast E-Tag (direct 0x0257)
- * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
- * and no external data
- */
-struct iavf_aqc_add_remove_mcast_etag {
- __le16 pv_seid;
- __le16 etag;
- u8 num_unicast_etags;
- u8 reserved[3];
- __le32 addr_high; /* address of array of 2-byte s-tags */
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_mcast_etag);
-
-struct iavf_aqc_add_remove_mcast_etag_completion {
- u8 reserved[4];
- __le16 mcast_etags_used;
- __le16 mcast_etags_free;
- __le32 addr_high;
- __le32 addr_low;
-
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_mcast_etag_completion);
-
-/* Update S/E-Tag (direct 0x0259) */
-struct iavf_aqc_update_tag {
- __le16 seid;
-#define IAVF_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
-#define IAVF_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
- IAVF_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
- __le16 old_tag;
- __le16 new_tag;
- u8 reserved[10];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_update_tag);
-
-struct iavf_aqc_update_tag_completion {
- u8 reserved[12];
- __le16 tags_used;
- __le16 tags_free;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_update_tag_completion);
-
-/* Add Control Packet filter (direct 0x025A)
- * Remove Control Packet filter (direct 0x025B)
- * uses the iavf_aqc_add_oveb_cloud,
- * and the generic direct completion structure
- */
-struct iavf_aqc_add_remove_control_packet_filter {
- u8 mac[6];
- __le16 etype;
- __le16 flags;
-#define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
-#define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
-#define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
-#define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
-#define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
- __le16 seid;
-#define IAVF_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
-#define IAVF_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
- IAVF_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
- __le16 queue;
- u8 reserved[2];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_control_packet_filter);
-
-struct iavf_aqc_add_remove_control_packet_filter_completion {
- __le16 mac_etype_used;
- __le16 etype_used;
- __le16 mac_etype_free;
- __le16 etype_free;
- u8 reserved[8];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_control_packet_filter_completion);
-
-/* Add Cloud filters (indirect 0x025C)
- * Remove Cloud filters (indirect 0x025D)
- * uses the iavf_aqc_add_remove_cloud_filters,
- * and the generic indirect completion structure
- */
-struct iavf_aqc_add_remove_cloud_filters {
- u8 num_filters;
- u8 reserved;
- __le16 seid;
-#define IAVF_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
-#define IAVF_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
- IAVF_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
- u8 big_buffer_flag;
-#define IAVF_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER 1
- u8 reserved2[3];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_cloud_filters);
-
-struct iavf_aqc_add_remove_cloud_filters_element_data {
- u8 outer_mac[6];
- u8 inner_mac[6];
- __le16 inner_vlan;
- union {
- struct {
- u8 reserved[12];
- u8 data[4];
- } v4;
- struct {
- u8 data[16];
- } v6;
- } ipaddr;
- __le16 flags;
-#define IAVF_AQC_ADD_CLOUD_FILTER_SHIFT 0
-#define IAVF_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
- IAVF_AQC_ADD_CLOUD_FILTER_SHIFT)
-/* 0x0000 reserved */
-#define IAVF_AQC_ADD_CLOUD_FILTER_OIP 0x0001
-/* 0x0002 reserved */
-#define IAVF_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
-#define IAVF_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
-/* 0x0005 reserved */
-#define IAVF_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
-/* 0x0007 reserved */
-/* 0x0008 reserved */
-#define IAVF_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
-#define IAVF_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
-#define IAVF_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
-#define IAVF_AQC_ADD_CLOUD_FILTER_IIP 0x000C
-/* 0x0010 to 0x0017 is for custom filters */
-
-#define IAVF_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
-#define IAVF_AQC_ADD_CLOUD_VNK_SHIFT 6
-#define IAVF_AQC_ADD_CLOUD_VNK_MASK 0x00C0
-#define IAVF_AQC_ADD_CLOUD_FLAGS_IPV4 0
-#define IAVF_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
-
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_IP 3
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
-
-#define IAVF_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
-#define IAVF_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
-#define IAVF_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
-
- __le32 tenant_id;
- u8 reserved[4];
- __le16 queue_number;
-#define IAVF_AQC_ADD_CLOUD_QUEUE_SHIFT 0
-#define IAVF_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
- IAVF_AQC_ADD_CLOUD_QUEUE_SHIFT)
- u8 reserved2[14];
- /* response section */
- u8 allocation_result;
-#define IAVF_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
-#define IAVF_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
- u8 response_reserved[7];
-};
-
-/* iavf_aqc_add_rm_cloud_filt_elem_ext is used when
- * IAVF_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER flag is set.
- */
-struct iavf_aqc_add_rm_cloud_filt_elem_ext {
- struct iavf_aqc_add_remove_cloud_filters_element_data element;
- u16 general_fields[32];
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30
-};
-
-struct iavf_aqc_remove_cloud_filters_completion {
- __le16 perfect_ovlan_used;
- __le16 perfect_ovlan_free;
- __le16 vlan_used;
- __le16 vlan_free;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_remove_cloud_filters_completion);
-
-/* Replace filter Command 0x025F
- * uses the iavf_aqc_replace_cloud_filters,
- * and the generic indirect completion structure
- */
-struct iavf_filter_data {
- u8 filter_type;
- u8 input[3];
-};
-
-struct iavf_aqc_replace_cloud_filters_cmd {
- u8 valid_flags;
-#define IAVF_AQC_REPLACE_L1_FILTER 0x0
-#define IAVF_AQC_REPLACE_CLOUD_FILTER 0x1
-#define IAVF_AQC_GET_CLOUD_FILTERS 0x2
-#define IAVF_AQC_MIRROR_CLOUD_FILTER 0x4
-#define IAVF_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8
- u8 old_filter_type;
- u8 new_filter_type;
- u8 tr_bit;
- u8 reserved[4];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-struct iavf_aqc_replace_cloud_filters_cmd_buf {
- u8 data[32];
-/* Filter type INPUT codes*/
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED (1 << 7UL)
-
-/* Field Vector offsets */
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12
-/* big FLU */
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14
-/* big FLU */
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15
-
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37
- struct iavf_filter_data filters[8];
-};
-
-/* Add Mirror Rule (indirect or direct 0x0260)
- * Delete Mirror Rule (indirect or direct 0x0261)
- * note: some rule types (4,5) do not use an external buffer.
- * take care to set the flags correctly.
- */
-struct iavf_aqc_add_delete_mirror_rule {
- __le16 seid;
- __le16 rule_type;
-#define IAVF_AQC_MIRROR_RULE_TYPE_SHIFT 0
-#define IAVF_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
- IAVF_AQC_MIRROR_RULE_TYPE_SHIFT)
-#define IAVF_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
-#define IAVF_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
-#define IAVF_AQC_MIRROR_RULE_TYPE_VLAN 3
-#define IAVF_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
-#define IAVF_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
- __le16 num_entries;
- __le16 destination; /* VSI for add, rule id for delete */
- __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_delete_mirror_rule);
-
-struct iavf_aqc_add_delete_mirror_rule_completion {
- u8 reserved[2];
- __le16 rule_id; /* only used on add */
- __le16 mirror_rules_used;
- __le16 mirror_rules_free;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_delete_mirror_rule_completion);
-
-/* Dynamic Device Personalization */
-struct iavf_aqc_write_personalization_profile {
- u8 flags;
- u8 reserved[3];
- __le32 profile_track_id;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_write_personalization_profile);
-
-struct iavf_aqc_write_ddp_resp {
- __le32 error_offset;
- __le32 error_info;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-struct iavf_aqc_get_applied_profiles {
- u8 flags;
-#define IAVF_AQC_GET_DDP_GET_CONF 0x1
-#define IAVF_AQC_GET_DDP_GET_RDPU_CONF 0x2
- u8 rsv[3];
- __le32 reserved;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_applied_profiles);
-
-/* DCB 0x03xx*/
-
-/* PFC Ignore (direct 0x0301)
- * the command and response use the same descriptor structure
- */
-struct iavf_aqc_pfc_ignore {
- u8 tc_bitmap;
- u8 command_flags; /* unused on response */
-#define IAVF_AQC_PFC_IGNORE_SET 0x80
-#define IAVF_AQC_PFC_IGNORE_CLEAR 0x0
- u8 reserved[14];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_pfc_ignore);
-
-/* DCB Update (direct 0x0302) uses the iavf_aq_desc structure
- * with no parameters
- */
-
-/* TX scheduler 0x04xx */
-
-/* Almost all the indirect commands use
- * this generic struct to pass the SEID in param0
- */
-struct iavf_aqc_tx_sched_ind {
- __le16 vsi_seid;
- u8 reserved[6];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_tx_sched_ind);
-
-/* Several commands respond with a set of queue set handles */
-struct iavf_aqc_qs_handles_resp {
- __le16 qs_handles[8];
-};
-
-/* Configure VSI BW limits (direct 0x0400) */
-struct iavf_aqc_configure_vsi_bw_limit {
- __le16 vsi_seid;
- u8 reserved[2];
- __le16 credit;
- u8 reserved1[2];
- u8 max_credit; /* 0-3, limit = 2^max */
- u8 reserved2[7];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_configure_vsi_bw_limit);
-
-/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
- * responds with iavf_aqc_qs_handles_resp
- */
-struct iavf_aqc_configure_vsi_ets_sla_bw_data {
- u8 tc_valid_bits;
- u8 reserved[15];
- __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
-
- /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
- __le16 tc_bw_max[2];
- u8 reserved1[28];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x40, iavf_aqc_configure_vsi_ets_sla_bw_data);
-
-/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
- * responds with iavf_aqc_qs_handles_resp
- */
-struct iavf_aqc_configure_vsi_tc_bw_data {
- u8 tc_valid_bits;
- u8 reserved[3];
- u8 tc_bw_credits[8];
- u8 reserved1[4];
- __le16 qs_handles[8];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_configure_vsi_tc_bw_data);
-
-/* Query vsi bw configuration (indirect 0x0408) */
-struct iavf_aqc_query_vsi_bw_config_resp {
- u8 tc_valid_bits;
- u8 tc_suspended_bits;
- u8 reserved[14];
- __le16 qs_handles[8];
- u8 reserved1[4];
- __le16 port_bw_limit;
- u8 reserved2[2];
- u8 max_bw; /* 0-3, limit = 2^max */
- u8 reserved3[23];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x40, iavf_aqc_query_vsi_bw_config_resp);
-
-/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
-struct iavf_aqc_query_vsi_ets_sla_config_resp {
- u8 tc_valid_bits;
- u8 reserved[3];
- u8 share_credits[8];
- __le16 credits[8];
-
- /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
- __le16 tc_bw_max[2];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_query_vsi_ets_sla_config_resp);
-
-/* Configure Switching Component Bandwidth Limit (direct 0x0410) */
-struct iavf_aqc_configure_switching_comp_bw_limit {
- __le16 seid;
- u8 reserved[2];
- __le16 credit;
- u8 reserved1[2];
- u8 max_bw; /* 0-3, limit = 2^max */
- u8 reserved2[7];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_configure_switching_comp_bw_limit);
-
-/* Enable Physical Port ETS (indirect 0x0413)
- * Modify Physical Port ETS (indirect 0x0414)
- * Disable Physical Port ETS (indirect 0x0415)
- */
-struct iavf_aqc_configure_switching_comp_ets_data {
- u8 reserved[4];
- u8 tc_valid_bits;
- u8 seepage;
-#define IAVF_AQ_ETS_SEEPAGE_EN_MASK 0x1
- u8 tc_strict_priority_flags;
- u8 reserved1[17];
- u8 tc_bw_share_credits[8];
- u8 reserved2[96];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x80, iavf_aqc_configure_switching_comp_ets_data);
-
-/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
-struct iavf_aqc_configure_switching_comp_ets_bw_limit_data {
- u8 tc_valid_bits;
- u8 reserved[15];
- __le16 tc_bw_credit[8];
-
- /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
- __le16 tc_bw_max[2];
- u8 reserved1[28];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x40,
- iavf_aqc_configure_switching_comp_ets_bw_limit_data);
-
-/* Configure Switching Component Bandwidth Allocation per Tc
- * (indirect 0x0417)
- */
-struct iavf_aqc_configure_switching_comp_bw_config_data {
- u8 tc_valid_bits;
- u8 reserved[2];
- u8 absolute_credits; /* bool */
- u8 tc_bw_share_credits[8];
- u8 reserved1[20];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_configure_switching_comp_bw_config_data);
-
-/* Query Switching Component Configuration (indirect 0x0418) */
-struct iavf_aqc_query_switching_comp_ets_config_resp {
- u8 tc_valid_bits;
- u8 reserved[35];
- __le16 port_bw_limit;
- u8 reserved1[2];
- u8 tc_bw_max; /* 0-3, limit = 2^max */
- u8 reserved2[23];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x40, iavf_aqc_query_switching_comp_ets_config_resp);
-
-/* Query PhysicalPort ETS Configuration (indirect 0x0419) */
-struct iavf_aqc_query_port_ets_config_resp {
- u8 reserved[4];
- u8 tc_valid_bits;
- u8 reserved1;
- u8 tc_strict_priority_bits;
- u8 reserved2;
- u8 tc_bw_share_credits[8];
- __le16 tc_bw_limits[8];
-
- /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
- __le16 tc_bw_max[2];
- u8 reserved3[32];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x44, iavf_aqc_query_port_ets_config_resp);
-
-/* Query Switching Component Bandwidth Allocation per Traffic Type
- * (indirect 0x041A)
- */
-struct iavf_aqc_query_switching_comp_bw_config_resp {
- u8 tc_valid_bits;
- u8 reserved[2];
- u8 absolute_credits_enable; /* bool */
- u8 tc_bw_share_credits[8];
- __le16 tc_bw_limits[8];
-
- /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
- __le16 tc_bw_max[2];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_query_switching_comp_bw_config_resp);
-
-/* Suspend/resume port TX traffic
- * (direct 0x041B and 0x041C) uses the generic SEID struct
- */
-
-/* Configure partition BW
- * (indirect 0x041D)
- */
-struct iavf_aqc_configure_partition_bw_data {
- __le16 pf_valid_bits;
- u8 min_bw[16]; /* guaranteed bandwidth */
- u8 max_bw[16]; /* bandwidth limit */
-};
-
-IAVF_CHECK_STRUCT_LEN(0x22, iavf_aqc_configure_partition_bw_data);
-
-/* Get and set the active HMC resource profile and status.
- * (direct 0x0500) and (direct 0x0501)
- */
-struct iavf_aq_get_set_hmc_resource_profile {
- u8 pm_profile;
- u8 pe_vf_enabled;
- u8 reserved[14];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aq_get_set_hmc_resource_profile);
-
-enum iavf_aq_hmc_profile {
- /* IAVF_HMC_PROFILE_NO_CHANGE = 0, reserved */
- IAVF_HMC_PROFILE_DEFAULT = 1,
- IAVF_HMC_PROFILE_FAVOR_VF = 2,
- IAVF_HMC_PROFILE_EQUAL = 3,
-};
-
-/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
-
-/* set in param0 for get phy abilities to report qualified modules */
-#define IAVF_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
-#define IAVF_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
-
-enum iavf_aq_phy_type {
- IAVF_PHY_TYPE_SGMII = 0x0,
- IAVF_PHY_TYPE_1000BASE_KX = 0x1,
- IAVF_PHY_TYPE_10GBASE_KX4 = 0x2,
- IAVF_PHY_TYPE_10GBASE_KR = 0x3,
- IAVF_PHY_TYPE_40GBASE_KR4 = 0x4,
- IAVF_PHY_TYPE_XAUI = 0x5,
- IAVF_PHY_TYPE_XFI = 0x6,
- IAVF_PHY_TYPE_SFI = 0x7,
- IAVF_PHY_TYPE_XLAUI = 0x8,
- IAVF_PHY_TYPE_XLPPI = 0x9,
- IAVF_PHY_TYPE_40GBASE_CR4_CU = 0xA,
- IAVF_PHY_TYPE_10GBASE_CR1_CU = 0xB,
- IAVF_PHY_TYPE_10GBASE_AOC = 0xC,
- IAVF_PHY_TYPE_40GBASE_AOC = 0xD,
- IAVF_PHY_TYPE_UNRECOGNIZED = 0xE,
- IAVF_PHY_TYPE_UNSUPPORTED = 0xF,
- IAVF_PHY_TYPE_100BASE_TX = 0x11,
- IAVF_PHY_TYPE_1000BASE_T = 0x12,
- IAVF_PHY_TYPE_10GBASE_T = 0x13,
- IAVF_PHY_TYPE_10GBASE_SR = 0x14,
- IAVF_PHY_TYPE_10GBASE_LR = 0x15,
- IAVF_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
- IAVF_PHY_TYPE_10GBASE_CR1 = 0x17,
- IAVF_PHY_TYPE_40GBASE_CR4 = 0x18,
- IAVF_PHY_TYPE_40GBASE_SR4 = 0x19,
- IAVF_PHY_TYPE_40GBASE_LR4 = 0x1A,
- IAVF_PHY_TYPE_1000BASE_SX = 0x1B,
- IAVF_PHY_TYPE_1000BASE_LX = 0x1C,
- IAVF_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
- IAVF_PHY_TYPE_20GBASE_KR2 = 0x1E,
- IAVF_PHY_TYPE_25GBASE_KR = 0x1F,
- IAVF_PHY_TYPE_25GBASE_CR = 0x20,
- IAVF_PHY_TYPE_25GBASE_SR = 0x21,
- IAVF_PHY_TYPE_25GBASE_LR = 0x22,
- IAVF_PHY_TYPE_25GBASE_AOC = 0x23,
- IAVF_PHY_TYPE_25GBASE_ACC = 0x24,
- IAVF_PHY_TYPE_MAX,
- IAVF_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,
- IAVF_PHY_TYPE_EMPTY = 0xFE,
- IAVF_PHY_TYPE_DEFAULT = 0xFF,
-};
-
-#define IAVF_LINK_SPEED_100MB_SHIFT 0x1
-#define IAVF_LINK_SPEED_1000MB_SHIFT 0x2
-#define IAVF_LINK_SPEED_10GB_SHIFT 0x3
-#define IAVF_LINK_SPEED_40GB_SHIFT 0x4
-#define IAVF_LINK_SPEED_20GB_SHIFT 0x5
-#define IAVF_LINK_SPEED_25GB_SHIFT 0x6
-
-enum iavf_aq_link_speed {
- IAVF_LINK_SPEED_UNKNOWN = 0,
- IAVF_LINK_SPEED_100MB = (1 << IAVF_LINK_SPEED_100MB_SHIFT),
- IAVF_LINK_SPEED_1GB = (1 << IAVF_LINK_SPEED_1000MB_SHIFT),
- IAVF_LINK_SPEED_10GB = (1 << IAVF_LINK_SPEED_10GB_SHIFT),
- IAVF_LINK_SPEED_40GB = (1 << IAVF_LINK_SPEED_40GB_SHIFT),
- IAVF_LINK_SPEED_20GB = (1 << IAVF_LINK_SPEED_20GB_SHIFT),
- IAVF_LINK_SPEED_25GB = (1 << IAVF_LINK_SPEED_25GB_SHIFT),
-};
-
-struct iavf_aqc_module_desc {
- u8 oui[3];
- u8 reserved1;
- u8 part_number[16];
- u8 revision[4];
- u8 reserved2[8];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_module_desc);
-
-struct iavf_aq_get_phy_abilities_resp {
- __le32 phy_type; /* bitmap using the above enum for offsets */
- u8 link_speed; /* bitmap using the above enum bit patterns */
- u8 abilities;
-#define IAVF_AQ_PHY_FLAG_PAUSE_TX 0x01
-#define IAVF_AQ_PHY_FLAG_PAUSE_RX 0x02
-#define IAVF_AQ_PHY_FLAG_LOW_POWER 0x04
-#define IAVF_AQ_PHY_LINK_ENABLED 0x08
-#define IAVF_AQ_PHY_AN_ENABLED 0x10
-#define IAVF_AQ_PHY_FLAG_MODULE_QUAL 0x20
-#define IAVF_AQ_PHY_FEC_ABILITY_KR 0x40
-#define IAVF_AQ_PHY_FEC_ABILITY_RS 0x80
- __le16 eee_capability;
-#define IAVF_AQ_EEE_100BASE_TX 0x0002
-#define IAVF_AQ_EEE_1000BASE_T 0x0004
-#define IAVF_AQ_EEE_10GBASE_T 0x0008
-#define IAVF_AQ_EEE_1000BASE_KX 0x0010
-#define IAVF_AQ_EEE_10GBASE_KX4 0x0020
-#define IAVF_AQ_EEE_10GBASE_KR 0x0040
- __le32 eeer_val;
- u8 d3_lpan;
-#define IAVF_AQ_SET_PHY_D3_LPAN_ENA 0x01
- u8 phy_type_ext;
-#define IAVF_AQ_PHY_TYPE_EXT_25G_KR 0x01
-#define IAVF_AQ_PHY_TYPE_EXT_25G_CR 0x02
-#define IAVF_AQ_PHY_TYPE_EXT_25G_SR 0x04
-#define IAVF_AQ_PHY_TYPE_EXT_25G_LR 0x08
-#define IAVF_AQ_PHY_TYPE_EXT_25G_AOC 0x10
-#define IAVF_AQ_PHY_TYPE_EXT_25G_ACC 0x20
- u8 fec_cfg_curr_mod_ext_info;
-#define IAVF_AQ_ENABLE_FEC_KR 0x01
-#define IAVF_AQ_ENABLE_FEC_RS 0x02
-#define IAVF_AQ_REQUEST_FEC_KR 0x04
-#define IAVF_AQ_REQUEST_FEC_RS 0x08
-#define IAVF_AQ_ENABLE_FEC_AUTO 0x10
-#define IAVF_AQ_FEC
-#define IAVF_AQ_MODULE_TYPE_EXT_MASK 0xE0
-#define IAVF_AQ_MODULE_TYPE_EXT_SHIFT 5
-
- u8 ext_comp_code;
- u8 phy_id[4];
- u8 module_type[3];
- u8 qualified_module_count;
-#define IAVF_AQ_PHY_MAX_QMS 16
- struct iavf_aqc_module_desc qualified_module[IAVF_AQ_PHY_MAX_QMS];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x218, iavf_aq_get_phy_abilities_resp);
-
-/* Set PHY Config (direct 0x0601) */
-struct iavf_aq_set_phy_config { /* same bits as above in all */
- __le32 phy_type;
- u8 link_speed;
- u8 abilities;
-/* bits 0-2 use the values from get_phy_abilities_resp */
-#define IAVF_AQ_PHY_ENABLE_LINK 0x08
-#define IAVF_AQ_PHY_ENABLE_AN 0x10
-#define IAVF_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
- __le16 eee_capability;
- __le32 eeer;
- u8 low_power_ctrl;
- u8 phy_type_ext;
- u8 fec_config;
-#define IAVF_AQ_SET_FEC_ABILITY_KR BIT(0)
-#define IAVF_AQ_SET_FEC_ABILITY_RS BIT(1)
-#define IAVF_AQ_SET_FEC_REQUEST_KR BIT(2)
-#define IAVF_AQ_SET_FEC_REQUEST_RS BIT(3)
-#define IAVF_AQ_SET_FEC_AUTO BIT(4)
-#define IAVF_AQ_PHY_FEC_CONFIG_SHIFT 0x0
-#define IAVF_AQ_PHY_FEC_CONFIG_MASK (0x1F << IAVF_AQ_PHY_FEC_CONFIG_SHIFT)
- u8 reserved;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aq_set_phy_config);
-
-/* Set MAC Config command data structure (direct 0x0603) */
-struct iavf_aq_set_mac_config {
- __le16 max_frame_size;
- u8 params;
-#define IAVF_AQ_SET_MAC_CONFIG_CRC_EN 0x04
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
- u8 tx_timer_priority; /* bitmap */
- __le16 tx_timer_value;
- __le16 fc_refresh_threshold;
- u8 reserved[8];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aq_set_mac_config);
-
-/* Restart Auto-Negotiation (direct 0x605) */
-struct iavf_aqc_set_link_restart_an {
- u8 command;
-#define IAVF_AQ_PHY_RESTART_AN 0x02
-#define IAVF_AQ_PHY_LINK_ENABLE 0x04
- u8 reserved[15];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_link_restart_an);
-
-/* Get Link Status cmd & response data structure (direct 0x0607) */
-struct iavf_aqc_get_link_status {
- __le16 command_flags; /* only field set on command */
-#define IAVF_AQ_LSE_MASK 0x3
-#define IAVF_AQ_LSE_NOP 0x0
-#define IAVF_AQ_LSE_DISABLE 0x2
-#define IAVF_AQ_LSE_ENABLE 0x3
-/* only response uses this flag */
-#define IAVF_AQ_LSE_IS_ENABLED 0x1
- u8 phy_type; /* iavf_aq_phy_type */
- u8 link_speed; /* iavf_aq_link_speed */
- u8 link_info;
-#define IAVF_AQ_LINK_UP 0x01 /* obsolete */
-#define IAVF_AQ_LINK_UP_FUNCTION 0x01
-#define IAVF_AQ_LINK_FAULT 0x02
-#define IAVF_AQ_LINK_FAULT_TX 0x04
-#define IAVF_AQ_LINK_FAULT_RX 0x08
-#define IAVF_AQ_LINK_FAULT_REMOTE 0x10
-#define IAVF_AQ_LINK_UP_PORT 0x20
-#define IAVF_AQ_MEDIA_AVAILABLE 0x40
-#define IAVF_AQ_SIGNAL_DETECT 0x80
- u8 an_info;
-#define IAVF_AQ_AN_COMPLETED 0x01
-#define IAVF_AQ_LP_AN_ABILITY 0x02
-#define IAVF_AQ_PD_FAULT 0x04
-#define IAVF_AQ_FEC_EN 0x08
-#define IAVF_AQ_PHY_LOW_POWER 0x10
-#define IAVF_AQ_LINK_PAUSE_TX 0x20
-#define IAVF_AQ_LINK_PAUSE_RX 0x40
-#define IAVF_AQ_QUALIFIED_MODULE 0x80
- u8 ext_info;
-#define IAVF_AQ_LINK_PHY_TEMP_ALARM 0x01
-#define IAVF_AQ_LINK_XCESSIVE_ERRORS 0x02
-#define IAVF_AQ_LINK_TX_SHIFT 0x02
-#define IAVF_AQ_LINK_TX_MASK (0x03 << IAVF_AQ_LINK_TX_SHIFT)
-#define IAVF_AQ_LINK_TX_ACTIVE 0x00
-#define IAVF_AQ_LINK_TX_DRAINED 0x01
-#define IAVF_AQ_LINK_TX_FLUSHED 0x03
-#define IAVF_AQ_LINK_FORCED_40G 0x10
-/* 25G Error Codes */
-#define IAVF_AQ_25G_NO_ERR 0X00
-#define IAVF_AQ_25G_NOT_PRESENT 0X01
-#define IAVF_AQ_25G_NVM_CRC_ERR 0X02
-#define IAVF_AQ_25G_SBUS_UCODE_ERR 0X03
-#define IAVF_AQ_25G_SERDES_UCODE_ERR 0X04
-#define IAVF_AQ_25G_NIMB_UCODE_ERR 0X05
- u8 loopback; /* use defines from iavf_aqc_set_lb_mode */
-/* Since firmware API 1.7 loopback field keeps power class info as well */
-#define IAVF_AQ_LOOPBACK_MASK 0x07
-#define IAVF_AQ_PWR_CLASS_SHIFT_LB 6
-#define IAVF_AQ_PWR_CLASS_MASK_LB (0x03 << IAVF_AQ_PWR_CLASS_SHIFT_LB)
- __le16 max_frame_size;
- u8 config;
-#define IAVF_AQ_CONFIG_FEC_KR_ENA 0x01
-#define IAVF_AQ_CONFIG_FEC_RS_ENA 0x02
-#define IAVF_AQ_CONFIG_CRC_ENA 0x04
-#define IAVF_AQ_CONFIG_PACING_MASK 0x78
- union {
- struct {
- u8 power_desc;
-#define IAVF_AQ_LINK_POWER_CLASS_1 0x00
-#define IAVF_AQ_LINK_POWER_CLASS_2 0x01
-#define IAVF_AQ_LINK_POWER_CLASS_3 0x02
-#define IAVF_AQ_LINK_POWER_CLASS_4 0x03
-#define IAVF_AQ_PWR_CLASS_MASK 0x03
- u8 reserved[4];
- };
- struct {
- u8 link_type[4];
- u8 link_type_ext;
- };
- };
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_link_status);
-
-/* Set event mask command (direct 0x613) */
-struct iavf_aqc_set_phy_int_mask {
- u8 reserved[8];
- __le16 event_mask;
-#define IAVF_AQ_EVENT_LINK_UPDOWN 0x0002
-#define IAVF_AQ_EVENT_MEDIA_NA 0x0004
-#define IAVF_AQ_EVENT_LINK_FAULT 0x0008
-#define IAVF_AQ_EVENT_PHY_TEMP_ALARM 0x0010
-#define IAVF_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
-#define IAVF_AQ_EVENT_SIGNAL_DETECT 0x0040
-#define IAVF_AQ_EVENT_AN_COMPLETED 0x0080
-#define IAVF_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
-#define IAVF_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
- u8 reserved1[6];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_phy_int_mask);
-
-/* Get Local AN advt register (direct 0x0614)
- * Set Local AN advt register (direct 0x0615)
- * Get Link Partner AN advt register (direct 0x0616)
- */
-struct iavf_aqc_an_advt_reg {
- __le32 local_an_reg0;
- __le16 local_an_reg1;
- u8 reserved[10];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_an_advt_reg);
-
-/* Set Loopback mode (0x0618) */
-struct iavf_aqc_set_lb_mode {
- u8 lb_level;
-#define IAVF_AQ_LB_NONE 0
-#define IAVF_AQ_LB_MAC 1
-#define IAVF_AQ_LB_SERDES 2
-#define IAVF_AQ_LB_PHY_INT 3
-#define IAVF_AQ_LB_PHY_EXT 4
-#define IAVF_AQ_LB_CPVL_PCS 5
-#define IAVF_AQ_LB_CPVL_EXT 6
-#define IAVF_AQ_LB_PHY_LOCAL 0x01
-#define IAVF_AQ_LB_PHY_REMOTE 0x02
-#define IAVF_AQ_LB_MAC_LOCAL 0x04
- u8 lb_type;
-#define IAVF_AQ_LB_LOCAL 0
-#define IAVF_AQ_LB_FAR 0x01
- u8 speed;
-#define IAVF_AQ_LB_SPEED_NONE 0
-#define IAVF_AQ_LB_SPEED_1G 1
-#define IAVF_AQ_LB_SPEED_10G 2
-#define IAVF_AQ_LB_SPEED_40G 3
-#define IAVF_AQ_LB_SPEED_20G 4
- u8 force_speed;
- u8 reserved[12];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_lb_mode);
-
-/* Set PHY Debug command (0x0622) */
-struct iavf_aqc_set_phy_debug {
- u8 command_flags;
-#define IAVF_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
-#define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
-#define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
- IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
-#define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
-#define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
-#define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
-/* Disable link manageability on a single port */
-#define IAVF_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
-/* Disable link manageability on all ports needs both bits 4 and 5 */
-#define IAVF_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
- u8 reserved[15];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_phy_debug);
-
-enum iavf_aq_phy_reg_type {
- IAVF_AQC_PHY_REG_INTERNAL = 0x1,
- IAVF_AQC_PHY_REG_EXERNAL_BASET = 0x2,
- IAVF_AQC_PHY_REG_EXERNAL_MODULE = 0x3
-};
-
-/* Run PHY Activity (0x0626) */
-struct iavf_aqc_run_phy_activity {
- __le16 activity_id;
- u8 flags;
- u8 reserved1;
- __le32 control;
- __le32 data;
- u8 reserved2[4];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_run_phy_activity);
-
-/* Set PHY Register command (0x0628) */
-/* Get PHY Register command (0x0629) */
-struct iavf_aqc_phy_register_access {
- u8 phy_interface;
-#define IAVF_AQ_PHY_REG_ACCESS_INTERNAL 0
-#define IAVF_AQ_PHY_REG_ACCESS_EXTERNAL 1
-#define IAVF_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2
- u8 dev_addres;
- u8 reserved1[2];
- __le32 reg_address;
- __le32 reg_value;
- u8 reserved2[4];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_phy_register_access);
-
-/* NVM Read command (indirect 0x0701)
- * NVM Erase commands (direct 0x0702)
- * NVM Update commands (indirect 0x0703)
- */
-struct iavf_aqc_nvm_update {
- u8 command_flags;
-#define IAVF_AQ_NVM_LAST_CMD 0x01
-#define IAVF_AQ_NVM_FLASH_ONLY 0x80
-#define IAVF_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1
-#define IAVF_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03
-#define IAVF_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
-#define IAVF_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01
- u8 module_pointer;
- __le16 length;
- __le32 offset;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_nvm_update);
-
-/* NVM Config Read (indirect 0x0704) */
-struct iavf_aqc_nvm_config_read {
- __le16 cmd_flags;
-#define IAVF_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
-#define IAVF_AQ_ANVM_READ_SINGLE_FEATURE 0
-#define IAVF_AQ_ANVM_READ_MULTIPLE_FEATURES 1
- __le16 element_count;
- __le16 element_id; /* Feature/field ID */
- __le16 element_id_msw; /* MSWord of field ID */
- __le32 address_high;
- __le32 address_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_nvm_config_read);
-
-/* NVM Config Write (indirect 0x0705) */
-struct iavf_aqc_nvm_config_write {
- __le16 cmd_flags;
- __le16 element_count;
- u8 reserved[4];
- __le32 address_high;
- __le32 address_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_nvm_config_write);
-
-/* Used for 0x0704 as well as for 0x0705 commands */
-#define IAVF_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
-#define IAVF_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
- (1 << IAVF_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
-#define IAVF_AQ_ANVM_FEATURE 0
-#define IAVF_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
-struct iavf_aqc_nvm_config_data_feature {
- __le16 feature_id;
-#define IAVF_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
-#define IAVF_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
-#define IAVF_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
- __le16 feature_options;
- __le16 feature_selection;
-};
-
-IAVF_CHECK_STRUCT_LEN(0x6, iavf_aqc_nvm_config_data_feature);
-
-struct iavf_aqc_nvm_config_data_immediate_field {
- __le32 field_id;
- __le32 field_value;
- __le16 field_options;
- __le16 reserved;
-};
-
-IAVF_CHECK_STRUCT_LEN(0xc, iavf_aqc_nvm_config_data_immediate_field);
-
-/* OEM Post Update (indirect 0x0720)
- * no command data struct used
- */
-struct iavf_aqc_nvm_oem_post_update {
-#define IAVF_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
- u8 sel_data;
- u8 reserved[7];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x8, iavf_aqc_nvm_oem_post_update);
-
-struct iavf_aqc_nvm_oem_post_update_buffer {
- u8 str_len;
- u8 dev_addr;
- __le16 eeprom_addr;
- u8 data[36];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x28, iavf_aqc_nvm_oem_post_update_buffer);
-
-/* Thermal Sensor (indirect 0x0721)
- * read or set thermal sensor configs and values
- * takes a sensor and command specific data buffer, not detailed here
- */
-struct iavf_aqc_thermal_sensor {
- u8 sensor_action;
-#define IAVF_AQ_THERMAL_SENSOR_READ_CONFIG 0
-#define IAVF_AQ_THERMAL_SENSOR_SET_CONFIG 1
-#define IAVF_AQ_THERMAL_SENSOR_READ_TEMP 2
- u8 reserved[7];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_thermal_sensor);
-
-/* Send to PF command (indirect 0x0801) id is only used by PF
- * Send to VF command (indirect 0x0802) id is only used by PF
- * Send to Peer PF command (indirect 0x0803)
- */
-struct iavf_aqc_pf_vf_message {
- __le32 id;
- u8 reserved[4];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_pf_vf_message);
-
-/* Alternate structure */
-
-/* Direct write (direct 0x0900)
- * Direct read (direct 0x0902)
- */
-struct iavf_aqc_alternate_write {
- __le32 address0;
- __le32 data0;
- __le32 address1;
- __le32 data1;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_write);
-
-/* Indirect write (indirect 0x0901)
- * Indirect read (indirect 0x0903)
- */
-
-struct iavf_aqc_alternate_ind_write {
- __le32 address;
- __le32 length;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_ind_write);
-
-/* Done alternate write (direct 0x0904)
- * uses iavf_aq_desc
- */
-struct iavf_aqc_alternate_write_done {
- __le16 cmd_flags;
-#define IAVF_AQ_ALTERNATE_MODE_BIOS_MASK 1
-#define IAVF_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
-#define IAVF_AQ_ALTERNATE_MODE_BIOS_UEFI 1
-#define IAVF_AQ_ALTERNATE_RESET_NEEDED 2
- u8 reserved[14];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_write_done);
-
-/* Set OEM mode (direct 0x0905) */
-struct iavf_aqc_alternate_set_mode {
- __le32 mode;
-#define IAVF_AQ_ALTERNATE_MODE_NONE 0
-#define IAVF_AQ_ALTERNATE_MODE_OEM 1
- u8 reserved[12];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_set_mode);
-
-/* Clear port Alternate RAM (direct 0x0906) uses iavf_aq_desc */
-
-/* async events 0x10xx */
-
-/* Lan Queue Overflow Event (direct, 0x1001) */
-struct iavf_aqc_lan_overflow {
- __le32 prtdcb_rupto;
- __le32 otx_ctl;
- u8 reserved[8];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lan_overflow);
-
-/* Get LLDP MIB (indirect 0x0A00) */
-struct iavf_aqc_lldp_get_mib {
- u8 type;
- u8 reserved1;
-#define IAVF_AQ_LLDP_MIB_TYPE_MASK 0x3
-#define IAVF_AQ_LLDP_MIB_LOCAL 0x0
-#define IAVF_AQ_LLDP_MIB_REMOTE 0x1
-#define IAVF_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
-#define IAVF_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
-#define IAVF_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
-#define IAVF_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
-#define IAVF_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
-#define IAVF_AQ_LLDP_TX_SHIFT 0x4
-#define IAVF_AQ_LLDP_TX_MASK (0x03 << IAVF_AQ_LLDP_TX_SHIFT)
-/* TX pause flags use IAVF_AQ_LINK_TX_* above */
- __le16 local_len;
- __le16 remote_len;
- u8 reserved2[2];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_get_mib);
-
-/* Configure LLDP MIB Change Event (direct 0x0A01)
- * also used for the event (with type in the command field)
- */
-struct iavf_aqc_lldp_update_mib {
- u8 command;
-#define IAVF_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
-#define IAVF_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
- u8 reserved[7];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_update_mib);
-
-/* Add LLDP TLV (indirect 0x0A02)
- * Delete LLDP TLV (indirect 0x0A04)
- */
-struct iavf_aqc_lldp_add_tlv {
- u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
- u8 reserved1[1];
- __le16 len;
- u8 reserved2[4];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_add_tlv);
-
-/* Update LLDP TLV (indirect 0x0A03) */
-struct iavf_aqc_lldp_update_tlv {
- u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
- u8 reserved;
- __le16 old_len;
- __le16 new_offset;
- __le16 new_len;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_update_tlv);
-
-/* Stop LLDP (direct 0x0A05) */
-struct iavf_aqc_lldp_stop {
- u8 command;
-#define IAVF_AQ_LLDP_AGENT_STOP 0x0
-#define IAVF_AQ_LLDP_AGENT_SHUTDOWN 0x1
- u8 reserved[15];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_stop);
-
-/* Start LLDP (direct 0x0A06) */
-
-struct iavf_aqc_lldp_start {
- u8 command;
-#define IAVF_AQ_LLDP_AGENT_START 0x1
- u8 reserved[15];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_start);
-
-/* Set DCB (direct 0x0303) */
-struct iavf_aqc_set_dcb_parameters {
- u8 command;
-#define IAVF_AQ_DCB_SET_AGENT 0x1
-#define IAVF_DCB_VALID 0x1
- u8 valid_flags;
- u8 reserved[14];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_dcb_parameters);
-
-/* Get CEE DCBX Oper Config (0x0A07)
- * uses the generic descriptor struct
- * returns below as indirect response
- */
-
-#define IAVF_AQC_CEE_APP_FCOE_SHIFT 0x0
-#define IAVF_AQC_CEE_APP_FCOE_MASK (0x7 << IAVF_AQC_CEE_APP_FCOE_SHIFT)
-#define IAVF_AQC_CEE_APP_ISCSI_SHIFT 0x3
-#define IAVF_AQC_CEE_APP_ISCSI_MASK (0x7 << IAVF_AQC_CEE_APP_ISCSI_SHIFT)
-#define IAVF_AQC_CEE_APP_FIP_SHIFT 0x8
-#define IAVF_AQC_CEE_APP_FIP_MASK (0x7 << IAVF_AQC_CEE_APP_FIP_SHIFT)
-
-#define IAVF_AQC_CEE_PG_STATUS_SHIFT 0x0
-#define IAVF_AQC_CEE_PG_STATUS_MASK (0x7 << IAVF_AQC_CEE_PG_STATUS_SHIFT)
-#define IAVF_AQC_CEE_PFC_STATUS_SHIFT 0x3
-#define IAVF_AQC_CEE_PFC_STATUS_MASK (0x7 << IAVF_AQC_CEE_PFC_STATUS_SHIFT)
-#define IAVF_AQC_CEE_APP_STATUS_SHIFT 0x8
-#define IAVF_AQC_CEE_APP_STATUS_MASK (0x7 << IAVF_AQC_CEE_APP_STATUS_SHIFT)
-#define IAVF_AQC_CEE_FCOE_STATUS_SHIFT 0x8
-#define IAVF_AQC_CEE_FCOE_STATUS_MASK (0x7 << IAVF_AQC_CEE_FCOE_STATUS_SHIFT)
-#define IAVF_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
-#define IAVF_AQC_CEE_ISCSI_STATUS_MASK (0x7 << IAVF_AQC_CEE_ISCSI_STATUS_SHIFT)
-#define IAVF_AQC_CEE_FIP_STATUS_SHIFT 0x10
-#define IAVF_AQC_CEE_FIP_STATUS_MASK (0x7 << IAVF_AQC_CEE_FIP_STATUS_SHIFT)
-
-/* struct iavf_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
- * word boundary layout issues, which the Linux compilers silently deal
- * with by adding padding, making the actual struct larger than designed.
- * However, the FW compiler for the NIC is less lenient and complains
- * about the struct. Hence, the struct defined here has an extra byte in
- * fields reserved3 and reserved4 to directly acknowledge that padding,
- * and the new length is used in the length check macro.
- */
-struct iavf_aqc_get_cee_dcb_cfg_v1_resp {
- u8 reserved1;
- u8 oper_num_tc;
- u8 oper_prio_tc[4];
- u8 reserved2;
- u8 oper_tc_bw[8];
- u8 oper_pfc_en;
- u8 reserved3[2];
- __le16 oper_app_prio;
- u8 reserved4[2];
- __le16 tlv_status;
-};
-
-IAVF_CHECK_STRUCT_LEN(0x18, iavf_aqc_get_cee_dcb_cfg_v1_resp);
-
-struct iavf_aqc_get_cee_dcb_cfg_resp {
- u8 oper_num_tc;
- u8 oper_prio_tc[4];
- u8 oper_tc_bw[8];
- u8 oper_pfc_en;
- __le16 oper_app_prio;
- __le32 tlv_status;
- u8 reserved[12];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_get_cee_dcb_cfg_resp);
-
-/* Set Local LLDP MIB (indirect 0x0A08)
- * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
- */
-struct iavf_aqc_lldp_set_local_mib {
-#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
-#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
- SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
-#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
-#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
-#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
- SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
-#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
- u8 type;
- u8 reserved0;
- __le16 length;
- u8 reserved1[4];
- __le32 address_high;
- __le32 address_low;
+struct iavf_aqc_lldp_set_local_mib {
+#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
+#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
+ SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
+#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
+#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
+#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
+ SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
+#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
+ u8 type;
+ u8 reserved0;
+ __le16 length;
+ u8 reserved1[4];
+ __le32 address_high;
+ __le32 address_low;
};
IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_set_local_mib);
IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_stop_start_specific_agent);
-/* Add Udp Tunnel command and completion (direct 0x0B00) */
-struct iavf_aqc_add_udp_tunnel {
- __le16 udp_port;
- u8 reserved0[3];
- u8 protocol_type;
-#define IAVF_AQC_TUNNEL_TYPE_VXLAN 0x00
-#define IAVF_AQC_TUNNEL_TYPE_NGE 0x01
-#define IAVF_AQC_TUNNEL_TYPE_TEREDO 0x10
-#define IAVF_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
- u8 reserved1[10];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_udp_tunnel);
-
-struct iavf_aqc_add_udp_tunnel_completion {
- __le16 udp_port;
- u8 filter_entry_index;
- u8 multiple_pfs;
-#define IAVF_AQC_SINGLE_PF 0x0
-#define IAVF_AQC_MULTIPLE_PFS 0x1
- u8 total_filters;
- u8 reserved[11];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_udp_tunnel_completion);
-
-/* remove UDP Tunnel command (0x0B01) */
-struct iavf_aqc_remove_udp_tunnel {
- u8 reserved[2];
- u8 index; /* 0 to 15 */
- u8 reserved2[13];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_remove_udp_tunnel);
-
-struct iavf_aqc_del_udp_tunnel_completion {
- __le16 udp_port;
- u8 index; /* 0 to 15 */
- u8 multiple_pfs;
- u8 total_filters_used;
- u8 reserved1[11];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_del_udp_tunnel_completion);
-
struct iavf_aqc_get_set_rss_key {
#define IAVF_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
#define IAVF_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
};
IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_set_rss_lut);
-
-/* tunnel key structure 0x0B10 */
-
-struct iavf_aqc_tunnel_key_structure {
- u8 key1_off;
- u8 key2_off;
- u8 key1_len; /* 0 to 15 */
- u8 key2_len; /* 0 to 15 */
- u8 flags;
-#define IAVF_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
-/* response flags */
-#define IAVF_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
-#define IAVF_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
-#define IAVF_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
- u8 network_key_index;
-#define IAVF_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
-#define IAVF_AQC_NETWORK_KEY_INDEX_NGE 0x1
-#define IAVF_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
-#define IAVF_AQC_NETWORK_KEY_INDEX_GRE 0x3
- u8 reserved[10];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_tunnel_key_structure);
-
-/* OEM mode commands (direct 0xFE0x) */
-struct iavf_aqc_oem_param_change {
- __le32 param_type;
-#define IAVF_AQ_OEM_PARAM_TYPE_PF_CTL 0
-#define IAVF_AQ_OEM_PARAM_TYPE_BW_CTL 1
-#define IAVF_AQ_OEM_PARAM_MAC 2
- __le32 param_value1;
- __le16 param_value2;
- u8 reserved[6];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_oem_param_change);
-
-struct iavf_aqc_oem_state_change {
- __le32 state;
-#define IAVF_AQ_OEM_STATE_LINK_DOWN 0x0
-#define IAVF_AQ_OEM_STATE_LINK_UP 0x1
- u8 reserved[12];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_oem_state_change);
-
-/* Initialize OCSD (0xFE02, direct) */
-struct iavf_aqc_opc_oem_ocsd_initialize {
- u8 type_status;
- u8 reserved1[3];
- __le32 ocsd_memory_block_addr_high;
- __le32 ocsd_memory_block_addr_low;
- __le32 requested_update_interval;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_opc_oem_ocsd_initialize);
-
-/* Initialize OCBB (0xFE03, direct) */
-struct iavf_aqc_opc_oem_ocbb_initialize {
- u8 type_status;
- u8 reserved1[3];
- __le32 ocbb_memory_block_addr_high;
- __le32 ocbb_memory_block_addr_low;
- u8 reserved2[4];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_opc_oem_ocbb_initialize);
-
-/* debug commands */
-
-/* get device id (0xFF00) uses the generic structure */
-
-/* set test more (0xFF01, internal) */
-
-struct iavf_acq_set_test_mode {
- u8 mode;
-#define IAVF_AQ_TEST_PARTIAL 0
-#define IAVF_AQ_TEST_FULL 1
-#define IAVF_AQ_TEST_NVM 2
- u8 reserved[3];
- u8 command;
-#define IAVF_AQ_TEST_OPEN 0
-#define IAVF_AQ_TEST_CLOSE 1
-#define IAVF_AQ_TEST_INC 2
- u8 reserved2[3];
- __le32 address_high;
- __le32 address_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_acq_set_test_mode);
-
-/* Debug Read Register command (0xFF03)
- * Debug Write Register command (0xFF04)
- */
-struct iavf_aqc_debug_reg_read_write {
- __le32 reserved;
- __le32 address;
- __le32 value_high;
- __le32 value_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_reg_read_write);
-
-/* Scatter/gather Reg Read (indirect 0xFF05)
- * Scatter/gather Reg Write (indirect 0xFF06)
- */
-
-/* iavf_aq_desc is used for the command */
-struct iavf_aqc_debug_reg_sg_element_data {
- __le32 address;
- __le32 value;
-};
-
-/* Debug Modify register (direct 0xFF07) */
-struct iavf_aqc_debug_modify_reg {
- __le32 address;
- __le32 value;
- __le32 clear_mask;
- __le32 set_mask;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_modify_reg);
-
-/* dump internal data (0xFF08, indirect) */
-
-#define IAVF_AQ_CLUSTER_ID_AUX 0
-#define IAVF_AQ_CLUSTER_ID_SWITCH_FLU 1
-#define IAVF_AQ_CLUSTER_ID_TXSCHED 2
-#define IAVF_AQ_CLUSTER_ID_HMC 3
-#define IAVF_AQ_CLUSTER_ID_MAC0 4
-#define IAVF_AQ_CLUSTER_ID_MAC1 5
-#define IAVF_AQ_CLUSTER_ID_MAC2 6
-#define IAVF_AQ_CLUSTER_ID_MAC3 7
-#define IAVF_AQ_CLUSTER_ID_DCB 8
-#define IAVF_AQ_CLUSTER_ID_EMP_MEM 9
-#define IAVF_AQ_CLUSTER_ID_PKT_BUF 10
-#define IAVF_AQ_CLUSTER_ID_ALTRAM 11
-
-struct iavf_aqc_debug_dump_internals {
- u8 cluster_id;
- u8 table_id;
- __le16 data_size;
- __le32 idx;
- __le32 address_high;
- __le32 address_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_dump_internals);
-
-struct iavf_aqc_debug_modify_internals {
- u8 cluster_id;
- u8 cluster_specific_params[7];
- __le32 address_high;
- __le32 address_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_modify_internals);
-
#endif /* _IAVF_ADMINQ_CMD_H_ */
IAVF_PTT_UNUSED_ENTRY(255)
};
-
/**
* iavf_validate_mac_addr - Validate unicast MAC address
* @mac_addr: pointer to MAC address
return status;
}
-/**
- * iavf_aq_rx_ctl_read_register - use FW to read from an Rx control register
- * @hw: pointer to the hw struct
- * @reg_addr: register address
- * @reg_val: ptr to register value
- * @cmd_details: pointer to command details structure or NULL
- *
- * Use the firmware to read the Rx control register,
- * especially useful if the Rx unit is under heavy pressure
- **/
-enum iavf_status iavf_aq_rx_ctl_read_register(struct iavf_hw *hw,
- u32 reg_addr, u32 *reg_val,
- struct iavf_asq_cmd_details *cmd_details)
-{
- struct iavf_aq_desc desc;
- struct iavf_aqc_rx_ctl_reg_read_write *cmd_resp =
- (struct iavf_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
- enum iavf_status status;
-
- if (reg_val == NULL)
- return IAVF_ERR_PARAM;
-
- iavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_rx_ctl_reg_read);
-
- cmd_resp->address = CPU_TO_LE32(reg_addr);
-
- status = iavf_asq_send_command(hw, &desc, NULL, 0, cmd_details);
-
- if (status == IAVF_SUCCESS)
- *reg_val = LE32_TO_CPU(cmd_resp->value);
-
- return status;
-}
-
-/**
- * iavf_read_rx_ctl - read from an Rx control register
- * @hw: pointer to the hw struct
- * @reg_addr: register address
- **/
-u32 iavf_read_rx_ctl(struct iavf_hw *hw, u32 reg_addr)
-{
- enum iavf_status status = IAVF_SUCCESS;
- bool use_register;
- int retry = 5;
- u32 val = 0;
-
- use_register = (((hw->aq.api_maj_ver == 1) &&
- (hw->aq.api_min_ver < 5)) ||
- (hw->mac.type == IAVF_MAC_X722));
- if (!use_register) {
-do_retry:
- status = iavf_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
- if (hw->aq.asq_last_status == IAVF_AQ_RC_EAGAIN && retry) {
- iavf_msec_delay(1);
- retry--;
- goto do_retry;
- }
- }
-
- /* if the AQ access failed, try the old-fashioned way */
- if (status || use_register)
- val = rd32(hw, reg_addr);
-
- return val;
-}
-
-/**
- * iavf_aq_rx_ctl_write_register
- * @hw: pointer to the hw struct
- * @reg_addr: register address
- * @reg_val: register value
- * @cmd_details: pointer to command details structure or NULL
- *
- * Use the firmware to write to an Rx control register,
- * especially useful if the Rx unit is under heavy pressure
- **/
-enum iavf_status iavf_aq_rx_ctl_write_register(struct iavf_hw *hw,
- u32 reg_addr, u32 reg_val,
- struct iavf_asq_cmd_details *cmd_details)
-{
- struct iavf_aq_desc desc;
- struct iavf_aqc_rx_ctl_reg_read_write *cmd =
- (struct iavf_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
- enum iavf_status status;
-
- iavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_rx_ctl_reg_write);
-
- cmd->address = CPU_TO_LE32(reg_addr);
- cmd->value = CPU_TO_LE32(reg_val);
-
- status = iavf_asq_send_command(hw, &desc, NULL, 0, cmd_details);
-
- return status;
-}
-
-/**
- * iavf_write_rx_ctl - write to an Rx control register
- * @hw: pointer to the hw struct
- * @reg_addr: register address
- * @reg_val: register value
- **/
-void iavf_write_rx_ctl(struct iavf_hw *hw, u32 reg_addr, u32 reg_val)
-{
- enum iavf_status status = IAVF_SUCCESS;
- bool use_register;
- int retry = 5;
-
- use_register = (((hw->aq.api_maj_ver == 1) &&
- (hw->aq.api_min_ver < 5)) ||
- (hw->mac.type == IAVF_MAC_X722));
- if (!use_register) {
-do_retry:
- status = iavf_aq_rx_ctl_write_register(hw, reg_addr,
- reg_val, NULL);
- if (hw->aq.asq_last_status == IAVF_AQ_RC_EAGAIN && retry) {
- iavf_msec_delay(1);
- retry--;
- goto do_retry;
- }
- }
-
- /* if the AQ access failed, try the old-fashioned way */
- if (status || use_register)
- wr32(hw, reg_addr, reg_val);
-}
-
-/**
- * iavf_aq_set_phy_register
- * @hw: pointer to the hw struct
- * @phy_select: select which phy should be accessed
- * @dev_addr: PHY device address
- * @reg_addr: PHY register address
- * @reg_val: new register value
- * @cmd_details: pointer to command details structure or NULL
- *
- * Write the external PHY register.
- **/
-enum iavf_status iavf_aq_set_phy_register(struct iavf_hw *hw,
- u8 phy_select, u8 dev_addr,
- u32 reg_addr, u32 reg_val,
- struct iavf_asq_cmd_details *cmd_details)
-{
- struct iavf_aq_desc desc;
- struct iavf_aqc_phy_register_access *cmd =
- (struct iavf_aqc_phy_register_access *)&desc.params.raw;
- enum iavf_status status;
-
- iavf_fill_default_direct_cmd_desc(&desc,
- iavf_aqc_opc_set_phy_register);
-
- cmd->phy_interface = phy_select;
- cmd->dev_addres = dev_addr;
- cmd->reg_address = CPU_TO_LE32(reg_addr);
- cmd->reg_value = CPU_TO_LE32(reg_val);
-
- status = iavf_asq_send_command(hw, &desc, NULL, 0, cmd_details);
-
- return status;
-}
-
-/**
- * iavf_aq_get_phy_register
- * @hw: pointer to the hw struct
- * @phy_select: select which phy should be accessed
- * @dev_addr: PHY device address
- * @reg_addr: PHY register address
- * @reg_val: read register value
- * @cmd_details: pointer to command details structure or NULL
- *
- * Read the external PHY register.
- **/
-enum iavf_status iavf_aq_get_phy_register(struct iavf_hw *hw,
- u8 phy_select, u8 dev_addr,
- u32 reg_addr, u32 *reg_val,
- struct iavf_asq_cmd_details *cmd_details)
-{
- struct iavf_aq_desc desc;
- struct iavf_aqc_phy_register_access *cmd =
- (struct iavf_aqc_phy_register_access *)&desc.params.raw;
- enum iavf_status status;
-
- iavf_fill_default_direct_cmd_desc(&desc,
- iavf_aqc_opc_get_phy_register);
-
- cmd->phy_interface = phy_select;
- cmd->dev_addres = dev_addr;
- cmd->reg_address = CPU_TO_LE32(reg_addr);
-
- status = iavf_asq_send_command(hw, &desc, NULL, 0, cmd_details);
- if (!status)
- *reg_val = LE32_TO_CPU(cmd->reg_value);
-
- return status;
-}
-
-
/**
* iavf_aq_send_msg_to_pf
* @hw: pointer to the hardware structure
hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
hw->dev_caps.dcb = msg->vf_cap_flags &
VIRTCHNL_VF_OFFLOAD_L2;
- hw->dev_caps.iwarp = (msg->vf_cap_flags &
- VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
for (i = 0; i < msg->num_vsis; i++) {
if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
iavf_memcpy(hw->mac.perm_addr,
IAVF_SUCCESS, NULL, 0, NULL);
}
-/**
- * iavf_aq_set_arp_proxy_config
- * @hw: pointer to the HW structure
- * @proxy_config: pointer to proxy config command table struct
- * @cmd_details: pointer to command details
- *
- * Set ARP offload parameters from pre-populated
- * iavf_aqc_arp_proxy_data struct
- **/
-enum iavf_status iavf_aq_set_arp_proxy_config(struct iavf_hw *hw,
- struct iavf_aqc_arp_proxy_data *proxy_config,
- struct iavf_asq_cmd_details *cmd_details)
-{
- struct iavf_aq_desc desc;
- enum iavf_status status;
-
- if (!proxy_config)
- return IAVF_ERR_PARAM;
-
- iavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_set_proxy_config);
-
- desc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_BUF);
- desc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_RD);
- desc.params.external.addr_high =
- CPU_TO_LE32(IAVF_HI_DWORD((u64)proxy_config));
- desc.params.external.addr_low =
- CPU_TO_LE32(IAVF_LO_DWORD((u64)proxy_config));
- desc.datalen = CPU_TO_LE16(sizeof(struct iavf_aqc_arp_proxy_data));
-
- status = iavf_asq_send_command(hw, &desc, proxy_config,
- sizeof(struct iavf_aqc_arp_proxy_data),
- cmd_details);
-
- return status;
-}
-
-/**
- * iavf_aq_opc_set_ns_proxy_table_entry
- * @hw: pointer to the HW structure
- * @ns_proxy_table_entry: pointer to NS table entry command struct
- * @cmd_details: pointer to command details
- *
- * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
- * from pre-populated iavf_aqc_ns_proxy_data struct
- **/
-enum iavf_status iavf_aq_set_ns_proxy_table_entry(struct iavf_hw *hw,
- struct iavf_aqc_ns_proxy_data *ns_proxy_table_entry,
- struct iavf_asq_cmd_details *cmd_details)
-{
- struct iavf_aq_desc desc;
- enum iavf_status status;
-
- if (!ns_proxy_table_entry)
- return IAVF_ERR_PARAM;
-
- iavf_fill_default_direct_cmd_desc(&desc,
- iavf_aqc_opc_set_ns_proxy_table_entry);
-
- desc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_BUF);
- desc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_RD);
- desc.params.external.addr_high =
- CPU_TO_LE32(IAVF_HI_DWORD((u64)ns_proxy_table_entry));
- desc.params.external.addr_low =
- CPU_TO_LE32(IAVF_LO_DWORD((u64)ns_proxy_table_entry));
- desc.datalen = CPU_TO_LE16(sizeof(struct iavf_aqc_ns_proxy_data));
-
- status = iavf_asq_send_command(hw, &desc, ns_proxy_table_entry,
- sizeof(struct iavf_aqc_ns_proxy_data),
- cmd_details);
-
- return status;
-}
-
-/**
- * iavf_aq_set_clear_wol_filter
- * @hw: pointer to the hw struct
- * @filter_index: index of filter to modify (0-7)
- * @filter: buffer containing filter to be set
- * @set_filter: true to set filter, false to clear filter
- * @no_wol_tco: if true, pass through packets cannot cause wake-up
- * if false, pass through packets may cause wake-up
- * @filter_valid: true if filter action is valid
- * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
- * @cmd_details: pointer to command details structure or NULL
- *
- * Set or clear WoL filter for port attached to the PF
- **/
-enum iavf_status iavf_aq_set_clear_wol_filter(struct iavf_hw *hw,
- u8 filter_index,
- struct iavf_aqc_set_wol_filter_data *filter,
- bool set_filter, bool no_wol_tco,
- bool filter_valid, bool no_wol_tco_valid,
- struct iavf_asq_cmd_details *cmd_details)
-{
- struct iavf_aq_desc desc;
- struct iavf_aqc_set_wol_filter *cmd =
- (struct iavf_aqc_set_wol_filter *)&desc.params.raw;
- enum iavf_status status;
- u16 cmd_flags = 0;
- u16 valid_flags = 0;
- u16 buff_len = 0;
-
- iavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_set_wol_filter);
-
- if (filter_index >= IAVF_AQC_MAX_NUM_WOL_FILTERS)
- return IAVF_ERR_PARAM;
- cmd->filter_index = CPU_TO_LE16(filter_index);
-
- if (set_filter) {
- if (!filter)
- return IAVF_ERR_PARAM;
-
- cmd_flags |= IAVF_AQC_SET_WOL_FILTER;
- cmd_flags |= IAVF_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
- }
-
- if (no_wol_tco)
- cmd_flags |= IAVF_AQC_SET_WOL_FILTER_NO_TCO_WOL;
- cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
-
- if (filter_valid)
- valid_flags |= IAVF_AQC_SET_WOL_FILTER_ACTION_VALID;
- if (no_wol_tco_valid)
- valid_flags |= IAVF_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
- cmd->valid_flags = CPU_TO_LE16(valid_flags);
-
- buff_len = sizeof(*filter);
- desc.datalen = CPU_TO_LE16(buff_len);
-
- desc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_BUF);
- desc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_RD);
-
- cmd->address_high = CPU_TO_LE32(IAVF_HI_DWORD((u64)filter));
- cmd->address_low = CPU_TO_LE32(IAVF_LO_DWORD((u64)filter));
-
- status = iavf_asq_send_command(hw, &desc, filter,
- buff_len, cmd_details);
-
- return status;
-}
-
-/**
- * iavf_aq_get_wake_event_reason
- * @hw: pointer to the hw struct
- * @wake_reason: return value, index of matching filter
- * @cmd_details: pointer to command details structure or NULL
- *
- * Get information for the reason of a Wake Up event
- **/
-enum iavf_status iavf_aq_get_wake_event_reason(struct iavf_hw *hw,
- u16 *wake_reason,
- struct iavf_asq_cmd_details *cmd_details)
-{
- struct iavf_aq_desc desc;
- struct iavf_aqc_get_wake_reason_completion *resp =
- (struct iavf_aqc_get_wake_reason_completion *)&desc.params.raw;
- enum iavf_status status;
-
- iavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_get_wake_reason);
-
- status = iavf_asq_send_command(hw, &desc, NULL, 0, cmd_details);
-
- if (status == IAVF_SUCCESS)
- *wake_reason = LE16_TO_CPU(resp->wake_reason);
-
- return status;
-}
-
/**
* iavf_aq_clear_all_wol_filters
* @hw: pointer to the hw struct
return status;
}
-
-/**
- * iavf_aq_write_ddp - Write dynamic device personalization (ddp)
- * @hw: pointer to the hw struct
- * @buff: command buffer (size in bytes = buff_size)
- * @buff_size: buffer size in bytes
- * @track_id: package tracking id
- * @error_offset: returns error offset
- * @error_info: returns error information
- * @cmd_details: pointer to command details structure or NULL
- **/
-enum
-iavf_status iavf_aq_write_ddp(struct iavf_hw *hw, void *buff,
- u16 buff_size, u32 track_id,
- u32 *error_offset, u32 *error_info,
- struct iavf_asq_cmd_details *cmd_details)
-{
- struct iavf_aq_desc desc;
- struct iavf_aqc_write_personalization_profile *cmd =
- (struct iavf_aqc_write_personalization_profile *)
- &desc.params.raw;
- struct iavf_aqc_write_ddp_resp *resp;
- enum iavf_status status;
-
- iavf_fill_default_direct_cmd_desc(&desc,
- iavf_aqc_opc_write_personalization_profile);
-
- desc.flags |= CPU_TO_LE16(IAVF_AQ_FLAG_BUF | IAVF_AQ_FLAG_RD);
- if (buff_size > IAVF_AQ_LARGE_BUF)
- desc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_LB);
-
- desc.datalen = CPU_TO_LE16(buff_size);
-
- cmd->profile_track_id = CPU_TO_LE32(track_id);
-
- status = iavf_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
- if (!status) {
- resp = (struct iavf_aqc_write_ddp_resp *)&desc.params.raw;
- if (error_offset)
- *error_offset = LE32_TO_CPU(resp->error_offset);
- if (error_info)
- *error_info = LE32_TO_CPU(resp->error_info);
- }
-
- return status;
-}
-
-/**
- * iavf_aq_get_ddp_list - Read dynamic device personalization (ddp)
- * @hw: pointer to the hw struct
- * @buff: command buffer (size in bytes = buff_size)
- * @buff_size: buffer size in bytes
- * @flags: AdminQ command flags
- * @cmd_details: pointer to command details structure or NULL
- **/
-enum
-iavf_status iavf_aq_get_ddp_list(struct iavf_hw *hw, void *buff,
- u16 buff_size, u8 flags,
- struct iavf_asq_cmd_details *cmd_details)
-{
- struct iavf_aq_desc desc;
- struct iavf_aqc_get_applied_profiles *cmd =
- (struct iavf_aqc_get_applied_profiles *)&desc.params.raw;
- enum iavf_status status;
-
- iavf_fill_default_direct_cmd_desc(&desc,
- iavf_aqc_opc_get_personalization_profile_list);
-
- desc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_BUF);
- if (buff_size > IAVF_AQ_LARGE_BUF)
- desc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_LB);
- desc.datalen = CPU_TO_LE16(buff_size);
-
- cmd->flags = flags;
-
- status = iavf_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
-
- return status;
-}
-
-/**
- * iavf_find_segment_in_package
- * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_IAVF)
- * @pkg_hdr: pointer to the package header to be searched
- *
- * This function searches a package file for a particular segment type. On
- * success it returns a pointer to the segment header, otherwise it will
- * return NULL.
- **/
-struct iavf_generic_seg_header *
-iavf_find_segment_in_package(u32 segment_type,
- struct iavf_package_header *pkg_hdr)
-{
- struct iavf_generic_seg_header *segment;
- u32 i;
-
- /* Search all package segments for the requested segment type */
- for (i = 0; i < pkg_hdr->segment_count; i++) {
- segment =
- (struct iavf_generic_seg_header *)((u8 *)pkg_hdr +
- pkg_hdr->segment_offset[i]);
-
- if (segment->type == segment_type)
- return segment;
- }
-
- return NULL;
-}
-
-/* Get section table in profile */
-#define IAVF_SECTION_TABLE(profile, sec_tbl) \
- do { \
- struct iavf_profile_segment *p = (profile); \
- u32 count; \
- u32 *nvm; \
- count = p->device_table_count; \
- nvm = (u32 *)&p->device_table[count]; \
- sec_tbl = (struct iavf_section_table *)&nvm[nvm[0] + 1]; \
- } while (0)
-
-/* Get section header in profile */
-#define IAVF_SECTION_HEADER(profile, offset) \
- (struct iavf_profile_section_header *)((u8 *)(profile) + (offset))
-
-/**
- * iavf_find_section_in_profile
- * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
- * @profile: pointer to the iavf segment header to be searched
- *
- * This function searches iavf segment for a particular section type. On
- * success it returns a pointer to the section header, otherwise it will
- * return NULL.
- **/
-struct iavf_profile_section_header *
-iavf_find_section_in_profile(u32 section_type,
- struct iavf_profile_segment *profile)
-{
- struct iavf_profile_section_header *sec;
- struct iavf_section_table *sec_tbl;
- u32 sec_off;
- u32 i;
-
- if (profile->header.type != SEGMENT_TYPE_IAVF)
- return NULL;
-
- IAVF_SECTION_TABLE(profile, sec_tbl);
-
- for (i = 0; i < sec_tbl->section_count; i++) {
- sec_off = sec_tbl->section_offset[i];
- sec = IAVF_SECTION_HEADER(profile, sec_off);
- if (sec->section.type == section_type)
- return sec;
- }
-
- return NULL;
-}
-
-/**
- * iavf_ddp_exec_aq_section - Execute generic AQ for DDP
- * @hw: pointer to the hw struct
- * @aq: command buffer containing all data to execute AQ
- **/
-STATIC enum
-iavf_status iavf_ddp_exec_aq_section(struct iavf_hw *hw,
- struct iavf_profile_aq_section *aq)
-{
- enum iavf_status status;
- struct iavf_aq_desc desc;
- u8 *msg = NULL;
- u16 msglen;
-
- iavf_fill_default_direct_cmd_desc(&desc, aq->opcode);
- desc.flags |= CPU_TO_LE16(aq->flags);
- iavf_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
- IAVF_NONDMA_TO_NONDMA);
-
- msglen = aq->datalen;
- if (msglen) {
- desc.flags |= CPU_TO_LE16((u16)(IAVF_AQ_FLAG_BUF |
- IAVF_AQ_FLAG_RD));
- if (msglen > IAVF_AQ_LARGE_BUF)
- desc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_LB);
- desc.datalen = CPU_TO_LE16(msglen);
- msg = &aq->data[0];
- }
-
- status = iavf_asq_send_command(hw, &desc, msg, msglen, NULL);
-
- if (status != IAVF_SUCCESS) {
- iavf_debug(hw, IAVF_DEBUG_PACKAGE,
- "unable to exec DDP AQ opcode %u, error %d\n",
- aq->opcode, status);
- return status;
- }
-
- /* copy returned desc to aq_buf */
- iavf_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
- IAVF_NONDMA_TO_NONDMA);
-
- return IAVF_SUCCESS;
-}
-
-/**
- * iavf_validate_profile
- * @hw: pointer to the hardware structure
- * @profile: pointer to the profile segment of the package to be validated
- * @track_id: package tracking id
- * @rollback: flag if the profile is for rollback.
- *
- * Validates supported devices and profile's sections.
- */
-STATIC enum iavf_status
-iavf_validate_profile(struct iavf_hw *hw, struct iavf_profile_segment *profile,
- u32 track_id, bool rollback)
-{
- struct iavf_profile_section_header *sec = NULL;
- enum iavf_status status = IAVF_SUCCESS;
- struct iavf_section_table *sec_tbl;
- u32 vendor_dev_id;
- u32 dev_cnt;
- u32 sec_off;
- u32 i;
-
- if (track_id == IAVF_DDP_TRACKID_INVALID) {
- iavf_debug(hw, IAVF_DEBUG_PACKAGE, "Invalid track_id\n");
- return IAVF_NOT_SUPPORTED;
- }
-
- dev_cnt = profile->device_table_count;
- for (i = 0; i < dev_cnt; i++) {
- vendor_dev_id = profile->device_table[i].vendor_dev_id;
- if ((vendor_dev_id >> 16) == IAVF_INTEL_VENDOR_ID &&
- hw->device_id == (vendor_dev_id & 0xFFFF))
- break;
- }
- if (dev_cnt && (i == dev_cnt)) {
- iavf_debug(hw, IAVF_DEBUG_PACKAGE,
- "Device doesn't support DDP\n");
- return IAVF_ERR_DEVICE_NOT_SUPPORTED;
- }
-
- IAVF_SECTION_TABLE(profile, sec_tbl);
-
- /* Validate sections types */
- for (i = 0; i < sec_tbl->section_count; i++) {
- sec_off = sec_tbl->section_offset[i];
- sec = IAVF_SECTION_HEADER(profile, sec_off);
- if (rollback) {
- if (sec->section.type == SECTION_TYPE_MMIO ||
- sec->section.type == SECTION_TYPE_AQ ||
- sec->section.type == SECTION_TYPE_RB_AQ) {
- iavf_debug(hw, IAVF_DEBUG_PACKAGE,
- "Not a roll-back package\n");
- return IAVF_NOT_SUPPORTED;
- }
- } else {
- if (sec->section.type == SECTION_TYPE_RB_AQ ||
- sec->section.type == SECTION_TYPE_RB_MMIO) {
- iavf_debug(hw, IAVF_DEBUG_PACKAGE,
- "Not an original package\n");
- return IAVF_NOT_SUPPORTED;
- }
- }
- }
-
- return status;
-}
-
-/**
- * iavf_write_profile
- * @hw: pointer to the hardware structure
- * @profile: pointer to the profile segment of the package to be downloaded
- * @track_id: package tracking id
- *
- * Handles the download of a complete package.
- */
-enum iavf_status
-iavf_write_profile(struct iavf_hw *hw, struct iavf_profile_segment *profile,
- u32 track_id)
-{
- enum iavf_status status = IAVF_SUCCESS;
- struct iavf_section_table *sec_tbl;
- struct iavf_profile_section_header *sec = NULL;
- struct iavf_profile_aq_section *ddp_aq;
- u32 section_size = 0;
- u32 offset = 0, info = 0;
- u32 sec_off;
- u32 i;
-
- status = iavf_validate_profile(hw, profile, track_id, false);
- if (status)
- return status;
-
- IAVF_SECTION_TABLE(profile, sec_tbl);
-
- for (i = 0; i < sec_tbl->section_count; i++) {
- sec_off = sec_tbl->section_offset[i];
- sec = IAVF_SECTION_HEADER(profile, sec_off);
- /* Process generic admin command */
- if (sec->section.type == SECTION_TYPE_AQ) {
- ddp_aq = (struct iavf_profile_aq_section *)&sec[1];
- status = iavf_ddp_exec_aq_section(hw, ddp_aq);
- if (status) {
- iavf_debug(hw, IAVF_DEBUG_PACKAGE,
- "Failed to execute aq: section %d, opcode %u\n",
- i, ddp_aq->opcode);
- break;
- }
- sec->section.type = SECTION_TYPE_RB_AQ;
- }
-
- /* Skip any non-mmio sections */
- if (sec->section.type != SECTION_TYPE_MMIO)
- continue;
-
- section_size = sec->section.size +
- sizeof(struct iavf_profile_section_header);
-
- /* Write MMIO section */
- status = iavf_aq_write_ddp(hw, (void *)sec, (u16)section_size,
- track_id, &offset, &info, NULL);
- if (status) {
- iavf_debug(hw, IAVF_DEBUG_PACKAGE,
- "Failed to write profile: section %d, offset %d, info %d\n",
- i, offset, info);
- break;
- }
- }
- return status;
-}
-
-/**
- * iavf_rollback_profile
- * @hw: pointer to the hardware structure
- * @profile: pointer to the profile segment of the package to be removed
- * @track_id: package tracking id
- *
- * Rolls back previously loaded package.
- */
-enum iavf_status
-iavf_rollback_profile(struct iavf_hw *hw, struct iavf_profile_segment *profile,
- u32 track_id)
-{
- struct iavf_profile_section_header *sec = NULL;
- enum iavf_status status = IAVF_SUCCESS;
- struct iavf_section_table *sec_tbl;
- u32 offset = 0, info = 0;
- u32 section_size = 0;
- u32 sec_off;
- int i;
-
- status = iavf_validate_profile(hw, profile, track_id, true);
- if (status)
- return status;
-
- IAVF_SECTION_TABLE(profile, sec_tbl);
-
- /* For rollback write sections in reverse */
- for (i = sec_tbl->section_count - 1; i >= 0; i--) {
- sec_off = sec_tbl->section_offset[i];
- sec = IAVF_SECTION_HEADER(profile, sec_off);
-
- /* Skip any non-rollback sections */
- if (sec->section.type != SECTION_TYPE_RB_MMIO)
- continue;
-
- section_size = sec->section.size +
- sizeof(struct iavf_profile_section_header);
-
- /* Write roll-back MMIO section */
- status = iavf_aq_write_ddp(hw, (void *)sec, (u16)section_size,
- track_id, &offset, &info, NULL);
- if (status) {
- iavf_debug(hw, IAVF_DEBUG_PACKAGE,
- "Failed to write profile: section %d, offset %d, info %d\n",
- i, offset, info);
- break;
- }
- }
- return status;
-}
-
-/**
- * iavf_add_pinfo_to_list
- * @hw: pointer to the hardware structure
- * @profile: pointer to the profile segment of the package
- * @profile_info_sec: buffer for information section
- * @track_id: package tracking id
- *
- * Register a profile to the list of loaded profiles.
- */
-enum iavf_status
-iavf_add_pinfo_to_list(struct iavf_hw *hw,
- struct iavf_profile_segment *profile,
- u8 *profile_info_sec, u32 track_id)
-{
- enum iavf_status status = IAVF_SUCCESS;
- struct iavf_profile_section_header *sec = NULL;
- struct iavf_profile_info *pinfo;
- u32 offset = 0, info = 0;
-
- sec = (struct iavf_profile_section_header *)profile_info_sec;
- sec->tbl_size = 1;
- sec->data_end = sizeof(struct iavf_profile_section_header) +
- sizeof(struct iavf_profile_info);
- sec->section.type = SECTION_TYPE_INFO;
- sec->section.offset = sizeof(struct iavf_profile_section_header);
- sec->section.size = sizeof(struct iavf_profile_info);
- pinfo = (struct iavf_profile_info *)(profile_info_sec +
- sec->section.offset);
- pinfo->track_id = track_id;
- pinfo->version = profile->version;
- pinfo->op = IAVF_DDP_ADD_TRACKID;
- iavf_memcpy(pinfo->name, profile->name, IAVF_DDP_NAME_SIZE,
- IAVF_NONDMA_TO_NONDMA);
-
- status = iavf_aq_write_ddp(hw, (void *)sec, sec->data_end,
- track_id, &offset, &info, NULL);
- return status;
-}
const char *iavf_aq_str(struct iavf_hw *hw, enum iavf_admin_queue_err aq_err);
const char *iavf_stat_str(struct iavf_hw *hw, enum iavf_status stat_err);
-
enum iavf_status iavf_set_mac_type(struct iavf_hw *hw);
extern struct iavf_rx_ptype_decoded iavf_ptype_lookup[];
void iavf_release_spinlock(struct iavf_spinlock *sp);
void iavf_destroy_spinlock(struct iavf_spinlock *sp);
-/* iavf_common for VF drivers*/
void iavf_parse_hw_config(struct iavf_hw *hw,
struct virtchnl_vf_resource *msg);
enum iavf_status iavf_reset(struct iavf_hw *hw);
enum iavf_status v_retval,
u8 *msg, u16 msglen,
struct iavf_asq_cmd_details *cmd_details);
-enum iavf_status iavf_set_filter_control(struct iavf_hw *hw,
- struct iavf_filter_control_settings *settings);
-enum iavf_status iavf_aq_add_rem_control_packet_filter(struct iavf_hw *hw,
- u8 *mac_addr, u16 ethtype, u16 flags,
- u16 vsi_seid, u16 queue, bool is_add,
- struct iavf_control_filter_stats *stats,
- struct iavf_asq_cmd_details *cmd_details);
enum iavf_status iavf_aq_debug_dump(struct iavf_hw *hw, u8 cluster_id,
u8 table_id, u32 start_index, u16 buff_size,
void *buff, u16 *ret_buff_size,
u8 *ret_next_table, u32 *ret_next_index,
struct iavf_asq_cmd_details *cmd_details);
-void iavf_add_filter_to_drop_tx_flow_control_frames(struct iavf_hw *hw,
- u16 vsi_seid);
-enum iavf_status iavf_aq_rx_ctl_read_register(struct iavf_hw *hw,
- u32 reg_addr, u32 *reg_val,
- struct iavf_asq_cmd_details *cmd_details);
-u32 iavf_read_rx_ctl(struct iavf_hw *hw, u32 reg_addr);
-enum iavf_status iavf_aq_rx_ctl_write_register(struct iavf_hw *hw,
- u32 reg_addr, u32 reg_val,
- struct iavf_asq_cmd_details *cmd_details);
-void iavf_write_rx_ctl(struct iavf_hw *hw, u32 reg_addr, u32 reg_val);
-enum iavf_status iavf_aq_set_phy_register(struct iavf_hw *hw,
- u8 phy_select, u8 dev_addr,
- u32 reg_addr, u32 reg_val,
- struct iavf_asq_cmd_details *cmd_details);
-enum iavf_status iavf_aq_get_phy_register(struct iavf_hw *hw,
- u8 phy_select, u8 dev_addr,
- u32 reg_addr, u32 *reg_val,
- struct iavf_asq_cmd_details *cmd_details);
-
-enum iavf_status iavf_aq_set_arp_proxy_config(struct iavf_hw *hw,
- struct iavf_aqc_arp_proxy_data *proxy_config,
- struct iavf_asq_cmd_details *cmd_details);
-enum iavf_status iavf_aq_set_ns_proxy_table_entry(struct iavf_hw *hw,
- struct iavf_aqc_ns_proxy_data *ns_proxy_table_entry,
- struct iavf_asq_cmd_details *cmd_details);
-enum iavf_status iavf_aq_set_clear_wol_filter(struct iavf_hw *hw,
- u8 filter_index,
- struct iavf_aqc_set_wol_filter_data *filter,
- bool set_filter, bool no_wol_tco,
- bool filter_valid, bool no_wol_tco_valid,
- struct iavf_asq_cmd_details *cmd_details);
-enum iavf_status iavf_aq_get_wake_event_reason(struct iavf_hw *hw,
- u16 *wake_reason,
- struct iavf_asq_cmd_details *cmd_details);
enum iavf_status iavf_aq_clear_all_wol_filters(struct iavf_hw *hw,
struct iavf_asq_cmd_details *cmd_details);
-enum iavf_status iavf_read_phy_register_clause22(struct iavf_hw *hw,
- u16 reg, u8 phy_addr, u16 *value);
-enum iavf_status iavf_write_phy_register_clause22(struct iavf_hw *hw,
- u16 reg, u8 phy_addr, u16 value);
-enum iavf_status iavf_read_phy_register_clause45(struct iavf_hw *hw,
- u8 page, u16 reg, u8 phy_addr, u16 *value);
-enum iavf_status iavf_write_phy_register_clause45(struct iavf_hw *hw,
- u8 page, u16 reg, u8 phy_addr, u16 value);
-enum iavf_status iavf_read_phy_register(struct iavf_hw *hw,
- u8 page, u16 reg, u8 phy_addr, u16 *value);
-enum iavf_status iavf_write_phy_register(struct iavf_hw *hw,
- u8 page, u16 reg, u8 phy_addr, u16 value);
-u8 iavf_get_phy_address(struct iavf_hw *hw, u8 dev_num);
-enum iavf_status iavf_blink_phy_link_led(struct iavf_hw *hw,
- u32 time, u32 interval);
-enum iavf_status iavf_aq_write_ddp(struct iavf_hw *hw, void *buff,
- u16 buff_size, u32 track_id,
- u32 *error_offset, u32 *error_info,
- struct iavf_asq_cmd_details *
- cmd_details);
-enum iavf_status iavf_aq_get_ddp_list(struct iavf_hw *hw, void *buff,
- u16 buff_size, u8 flags,
- struct iavf_asq_cmd_details *
- cmd_details);
-struct iavf_generic_seg_header *
-iavf_find_segment_in_package(u32 segment_type,
- struct iavf_package_header *pkg_header);
-struct iavf_profile_section_header *
-iavf_find_section_in_profile(u32 section_type,
- struct iavf_profile_segment *profile);
-enum iavf_status
-iavf_write_profile(struct iavf_hw *hw, struct iavf_profile_segment *iavf_seg,
- u32 track_id);
-enum iavf_status
-iavf_rollback_profile(struct iavf_hw *hw, struct iavf_profile_segment *iavf_seg,
- u32 track_id);
-enum iavf_status
-iavf_add_pinfo_to_list(struct iavf_hw *hw,
- struct iavf_profile_segment *profile,
- u8 *profile_info_sec, u32 track_id);
#endif /* _IAVF_PROTOTYPE_H_ */
#endif /* BIT_ULL */
#endif /* LINUX_MACROS */
-#ifndef IAVF_MASK
/* IAVF_MASK is a macro used on 32 bit registers */
#define IAVF_MASK(mask, shift) (mask << shift)
-#endif
#define IAVF_MAX_PF 16
#define IAVF_MAX_PF_VSI 64
#define IAVF_MAX_VSI_QP 16
#define IAVF_MAX_VF_VSI 3
#define IAVF_MAX_CHAINED_RX_BUFFERS 5
-#define IAVF_MAX_PF_UDP_OFFLOAD_PORTS 16
/* something less than 1 minute */
#define IAVF_HEARTBEAT_TIMEOUT (HZ * 50)
-/* Max default timeout in ms, */
-#define IAVF_MAX_NVM_TIMEOUT 18000
-
-/* Max timeout in ms for the phy to respond */
-#define IAVF_MAX_PHY_TIMEOUT 500
/* Check whether address is multicast. */
#define IAVF_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
((((u8 *)(address))[0] == ((u8)0xff)) && \
(((u8 *)(address))[1] == ((u8)0xff)))
-/* Switch from ms to the 1usec global time (this is the GTIME resolution) */
-#define IAVF_MS_TO_GTIME(time) ((time) * 1000)
/* forward declaration */
struct iavf_hw;
IAVF_MAC_GENERIC,
};
-enum iavf_media_type {
- IAVF_MEDIA_TYPE_UNKNOWN = 0,
- IAVF_MEDIA_TYPE_FIBER,
- IAVF_MEDIA_TYPE_BASET,
- IAVF_MEDIA_TYPE_BACKPLANE,
- IAVF_MEDIA_TYPE_CX4,
- IAVF_MEDIA_TYPE_DA,
- IAVF_MEDIA_TYPE_VIRTUAL
-};
-
-enum iavf_fc_mode {
- IAVF_FC_NONE = 0,
- IAVF_FC_RX_PAUSE,
- IAVF_FC_TX_PAUSE,
- IAVF_FC_FULL,
- IAVF_FC_PFC,
- IAVF_FC_DEFAULT
-};
-
-enum iavf_set_fc_aq_failures {
- IAVF_SET_FC_AQ_FAIL_NONE = 0,
- IAVF_SET_FC_AQ_FAIL_GET = 1,
- IAVF_SET_FC_AQ_FAIL_SET = 2,
- IAVF_SET_FC_AQ_FAIL_UPDATE = 4,
- IAVF_SET_FC_AQ_FAIL_SET_UPDATE = 6
-};
-
enum iavf_vsi_type {
IAVF_VSI_MAIN = 0,
IAVF_VSI_VMDQ1 = 1,
IAVF_QUEUE_TYPE_UNKNOWN
};
-struct iavf_link_status {
- enum iavf_aq_phy_type phy_type;
- enum iavf_aq_link_speed link_speed;
- u8 link_info;
- u8 an_info;
- u8 req_fec_info;
- u8 fec_info;
- u8 ext_info;
- u8 loopback;
- /* is Link Status Event notification to SW enabled */
- bool lse_enable;
- u16 max_frame_size;
- bool crc_enable;
- u8 pacing;
- u8 requested_speeds;
- u8 module_type[3];
- /* 1st byte: module identifier */
-#define IAVF_MODULE_TYPE_SFP 0x03
-#define IAVF_MODULE_TYPE_QSFP 0x0D
- /* 2nd byte: ethernet compliance codes for 10/40G */
-#define IAVF_MODULE_TYPE_40G_ACTIVE 0x01
-#define IAVF_MODULE_TYPE_40G_LR4 0x02
-#define IAVF_MODULE_TYPE_40G_SR4 0x04
-#define IAVF_MODULE_TYPE_40G_CR4 0x08
-#define IAVF_MODULE_TYPE_10G_BASE_SR 0x10
-#define IAVF_MODULE_TYPE_10G_BASE_LR 0x20
-#define IAVF_MODULE_TYPE_10G_BASE_LRM 0x40
-#define IAVF_MODULE_TYPE_10G_BASE_ER 0x80
- /* 3rd byte: ethernet compliance codes for 1G */
-#define IAVF_MODULE_TYPE_1000BASE_SX 0x01
-#define IAVF_MODULE_TYPE_1000BASE_LX 0x02
-#define IAVF_MODULE_TYPE_1000BASE_CX 0x04
-#define IAVF_MODULE_TYPE_1000BASE_T 0x08
-};
-
-struct iavf_phy_info {
- struct iavf_link_status link_info;
- struct iavf_link_status link_info_old;
- bool get_link_info;
- enum iavf_media_type media_type;
- /* all the phy types the NVM is capable of */
- u64 phy_types;
-};
-
-#define IAVF_CAP_PHY_TYPE_SGMII BIT_ULL(IAVF_PHY_TYPE_SGMII)
-#define IAVF_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(IAVF_PHY_TYPE_1000BASE_KX)
-#define IAVF_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(IAVF_PHY_TYPE_10GBASE_KX4)
-#define IAVF_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(IAVF_PHY_TYPE_10GBASE_KR)
-#define IAVF_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(IAVF_PHY_TYPE_40GBASE_KR4)
-#define IAVF_CAP_PHY_TYPE_XAUI BIT_ULL(IAVF_PHY_TYPE_XAUI)
-#define IAVF_CAP_PHY_TYPE_XFI BIT_ULL(IAVF_PHY_TYPE_XFI)
-#define IAVF_CAP_PHY_TYPE_SFI BIT_ULL(IAVF_PHY_TYPE_SFI)
-#define IAVF_CAP_PHY_TYPE_XLAUI BIT_ULL(IAVF_PHY_TYPE_XLAUI)
-#define IAVF_CAP_PHY_TYPE_XLPPI BIT_ULL(IAVF_PHY_TYPE_XLPPI)
-#define IAVF_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(IAVF_PHY_TYPE_40GBASE_CR4_CU)
-#define IAVF_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(IAVF_PHY_TYPE_10GBASE_CR1_CU)
-#define IAVF_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(IAVF_PHY_TYPE_10GBASE_AOC)
-#define IAVF_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(IAVF_PHY_TYPE_40GBASE_AOC)
-#define IAVF_CAP_PHY_TYPE_100BASE_TX BIT_ULL(IAVF_PHY_TYPE_100BASE_TX)
-#define IAVF_CAP_PHY_TYPE_1000BASE_T BIT_ULL(IAVF_PHY_TYPE_1000BASE_T)
-#define IAVF_CAP_PHY_TYPE_10GBASE_T BIT_ULL(IAVF_PHY_TYPE_10GBASE_T)
-#define IAVF_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(IAVF_PHY_TYPE_10GBASE_SR)
-#define IAVF_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(IAVF_PHY_TYPE_10GBASE_LR)
-#define IAVF_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(IAVF_PHY_TYPE_10GBASE_SFPP_CU)
-#define IAVF_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(IAVF_PHY_TYPE_10GBASE_CR1)
-#define IAVF_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(IAVF_PHY_TYPE_40GBASE_CR4)
-#define IAVF_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(IAVF_PHY_TYPE_40GBASE_SR4)
-#define IAVF_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(IAVF_PHY_TYPE_40GBASE_LR4)
-#define IAVF_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(IAVF_PHY_TYPE_1000BASE_SX)
-#define IAVF_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(IAVF_PHY_TYPE_1000BASE_LX)
-#define IAVF_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
- BIT_ULL(IAVF_PHY_TYPE_1000BASE_T_OPTICAL)
-#define IAVF_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(IAVF_PHY_TYPE_20GBASE_KR2)
-/*
- * Defining the macro IAVF_TYPE_OFFSET to implement a bit shift for some
- * PHY types. There is an unused bit (31) in the IAVF_CAP_PHY_TYPE_* bit
- * fields but no corresponding gap in the iavf_aq_phy_type enumeration. So,
- * a shift is needed to adjust for this with values larger than 31. The
- * only affected values are IAVF_PHY_TYPE_25GBASE_*.
- */
-#define IAVF_PHY_TYPE_OFFSET 1
-#define IAVF_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(IAVF_PHY_TYPE_25GBASE_KR + \
- IAVF_PHY_TYPE_OFFSET)
-#define IAVF_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(IAVF_PHY_TYPE_25GBASE_CR + \
- IAVF_PHY_TYPE_OFFSET)
-#define IAVF_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(IAVF_PHY_TYPE_25GBASE_SR + \
- IAVF_PHY_TYPE_OFFSET)
-#define IAVF_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(IAVF_PHY_TYPE_25GBASE_LR + \
- IAVF_PHY_TYPE_OFFSET)
-#define IAVF_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(IAVF_PHY_TYPE_25GBASE_AOC + \
- IAVF_PHY_TYPE_OFFSET)
-#define IAVF_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(IAVF_PHY_TYPE_25GBASE_ACC + \
- IAVF_PHY_TYPE_OFFSET)
#define IAVF_HW_CAP_MAX_GPIO 30
#define IAVF_HW_CAP_MDIO_PORT_MODE_MDIO 0
#define IAVF_HW_CAP_MDIO_PORT_MODE_I2C 1
/* Capabilities of a PF or a VF or the whole device */
struct iavf_hw_capabilities {
- u32 switch_mode;
-#define IAVF_NVM_IMAGE_TYPE_EVB 0x0
-#define IAVF_NVM_IMAGE_TYPE_CLOUD 0x2
-#define IAVF_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
-
- u32 management_mode;
- u32 mng_protocols_over_mctp;
-#define IAVF_MNG_PROTOCOL_PLDM 0x2
-#define IAVF_MNG_PROTOCOL_OEM_COMMANDS 0x4
-#define IAVF_MNG_PROTOCOL_NCSI 0x8
- u32 npar_enable;
- u32 os2bmc;
- u32 valid_functions;
- bool sr_iov_1_1;
- bool vmdq;
- bool evb_802_1_qbg; /* Edge Virtual Bridging */
- bool evb_802_1_qbh; /* Bridge Port Extension */
+ /* Cloud filter modes:
+ * Mode1: Filter on L4 port only
+ * Mode2: Filter for non-tunneled traffic
+ * Mode3: Filter for tunnel traffic
+ */
+#define IAVF_CLOUD_FILTER_MODE1 0x6
+#define IAVF_CLOUD_FILTER_MODE2 0x7
+#define IAVF_CLOUD_FILTER_MODE3 0x8
+#define IAVF_SWITCH_MODE_MASK 0xF
+
bool dcb;
bool fcoe;
- bool iscsi; /* Indicates iSCSI enabled */
- bool flex10_enable;
- bool flex10_capable;
- u32 flex10_mode;
-#define IAVF_FLEX10_MODE_UNKNOWN 0x0
-#define IAVF_FLEX10_MODE_DCC 0x1
-#define IAVF_FLEX10_MODE_DCI 0x2
-
- u32 flex10_status;
-#define IAVF_FLEX10_STATUS_DCC_ERROR 0x1
-#define IAVF_FLEX10_STATUS_VC_MODE 0x2
-
- bool sec_rev_disabled;
- bool update_disabled;
-#define IAVF_NVM_MGMT_SEC_REV_DISABLED 0x1
-#define IAVF_NVM_MGMT_UPDATE_DISABLED 0x2
-
- bool mgmt_cem;
- bool ieee_1588;
bool iwarp;
- bool fd;
- u32 fd_filters_guaranteed;
- u32 fd_filters_best_effort;
- bool rss;
- u32 rss_table_size;
- u32 rss_table_entry_width;
- bool led[IAVF_HW_CAP_MAX_GPIO];
- bool sdp[IAVF_HW_CAP_MAX_GPIO];
- u32 nvm_image_type;
- u32 num_flow_director_filters;
- u32 num_vfs;
- u32 vf_base_id;
u32 num_vsis;
u32 num_rx_qp;
u32 num_tx_qp;
u32 base_queue;
- u32 num_msix_vectors;
u32 num_msix_vectors_vf;
- u32 led_pin_num;
- u32 sdp_pin_num;
- u32 mdio_port_num;
- u32 mdio_port_mode;
- u8 rx_buf_chain_len;
- u32 enabled_tcmap;
- u32 maxtc;
- u64 wr_csr_prot;
bool apm_wol_support;
enum iavf_acpi_programming_method acpi_prog_method;
bool proxy_support;
u16 max_fcoeq;
};
-enum iavf_aq_resources_ids {
- IAVF_NVM_RESOURCE_ID = 1
-};
-
-enum iavf_aq_resource_access_type {
- IAVF_RESOURCE_READ = 1,
- IAVF_RESOURCE_WRITE
-};
+#define IAVF_NVM_EXEC_GET_AQ_RESULT 0x0
+#define IAVF_NVM_EXEC_FEATURES 0xe
+#define IAVF_NVM_EXEC_STATUS 0xf
-struct iavf_nvm_info {
- u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
- u32 timeout; /* [ms] */
- u16 sr_size; /* Shadow RAM size in words */
- bool blank_nvm_mode; /* is NVM empty (no FW present)*/
- u16 version; /* NVM package version */
- u32 eetrack; /* NVM data version */
- u32 oem_ver; /* OEM version info */
-};
+/* NVMUpdate features API */
+#define IAVF_NVMUPD_FEATURES_API_VER_MAJOR 0
+#define IAVF_NVMUPD_FEATURES_API_VER_MINOR 14
+#define IAVF_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN 12
-/* definitions used in NVM update support */
-
-enum iavf_nvmupd_cmd {
- IAVF_NVMUPD_INVALID,
- IAVF_NVMUPD_READ_CON,
- IAVF_NVMUPD_READ_SNT,
- IAVF_NVMUPD_READ_LCB,
- IAVF_NVMUPD_READ_SA,
- IAVF_NVMUPD_WRITE_ERA,
- IAVF_NVMUPD_WRITE_CON,
- IAVF_NVMUPD_WRITE_SNT,
- IAVF_NVMUPD_WRITE_LCB,
- IAVF_NVMUPD_WRITE_SA,
- IAVF_NVMUPD_CSUM_CON,
- IAVF_NVMUPD_CSUM_SA,
- IAVF_NVMUPD_CSUM_LCB,
- IAVF_NVMUPD_STATUS,
- IAVF_NVMUPD_EXEC_AQ,
- IAVF_NVMUPD_GET_AQ_RESULT,
- IAVF_NVMUPD_GET_AQ_EVENT,
-};
-
-enum iavf_nvmupd_state {
- IAVF_NVMUPD_STATE_INIT,
- IAVF_NVMUPD_STATE_READING,
- IAVF_NVMUPD_STATE_WRITING,
- IAVF_NVMUPD_STATE_INIT_WAIT,
- IAVF_NVMUPD_STATE_WRITE_WAIT,
- IAVF_NVMUPD_STATE_ERROR
-};
+#define IAVF_NVMUPD_FEATURE_FLAT_NVM_SUPPORT BIT(0)
-/* nvm_access definition and its masks/shifts need to be accessible to
- * application, core driver, and shared code. Where is the right file?
- */
-#define IAVF_NVM_READ 0xB
-#define IAVF_NVM_WRITE 0xC
-
-#define IAVF_NVM_MOD_PNT_MASK 0xFF
-
-#define IAVF_NVM_TRANS_SHIFT 8
-#define IAVF_NVM_TRANS_MASK (0xf << IAVF_NVM_TRANS_SHIFT)
-#define IAVF_NVM_PRESERVATION_FLAGS_SHIFT 12
-#define IAVF_NVM_PRESERVATION_FLAGS_MASK \
- (0x3 << IAVF_NVM_PRESERVATION_FLAGS_SHIFT)
-#define IAVF_NVM_PRESERVATION_FLAGS_SELECTED 0x01
-#define IAVF_NVM_PRESERVATION_FLAGS_ALL 0x02
-#define IAVF_NVM_CON 0x0
-#define IAVF_NVM_SNT 0x1
-#define IAVF_NVM_LCB 0x2
-#define IAVF_NVM_SA (IAVF_NVM_SNT | IAVF_NVM_LCB)
-#define IAVF_NVM_ERA 0x4
-#define IAVF_NVM_CSUM 0x8
-#define IAVF_NVM_AQE 0xe
-#define IAVF_NVM_EXEC 0xf
-
-#define IAVF_NVM_ADAPT_SHIFT 16
-#define IAVF_NVM_ADAPT_MASK (0xffffULL << IAVF_NVM_ADAPT_SHIFT)
-
-#define IAVF_NVMUPD_MAX_DATA 4096
-#define IAVF_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
-
-struct iavf_nvm_access {
- u32 command;
- u32 config;
- u32 offset; /* in bytes */
- u32 data_size; /* in bytes */
- u8 data[1];
+struct iavf_nvmupd_features {
+ u8 major;
+ u8 minor;
+ u16 size;
+ u8 features[IAVF_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN];
};
-/* (Q)SFP module access definitions */
-#define IAVF_I2C_EEPROM_DEV_ADDR 0xA0
-#define IAVF_I2C_EEPROM_DEV_ADDR2 0xA2
-#define IAVF_MODULE_TYPE_ADDR 0x00
-#define IAVF_MODULE_REVISION_ADDR 0x01
-#define IAVF_MODULE_SFF_8472_COMP 0x5E
-#define IAVF_MODULE_SFF_8472_SWAP 0x5C
-#define IAVF_MODULE_SFF_ADDR_MODE 0x04
#define IAVF_MODULE_SFF_DIAG_CAPAB 0x40
-#define IAVF_MODULE_TYPE_QSFP_PLUS 0x0D
-#define IAVF_MODULE_TYPE_QSFP28 0x11
-#define IAVF_MODULE_QSFP_MAX_LEN 640
-
/* PCI bus types */
enum iavf_bus_type {
iavf_bus_type_unknown = 0,
u16 bus_id;
};
-/* Flow control (FC) parameters */
-struct iavf_fc_info {
- enum iavf_fc_mode current_mode; /* FC mode in effect */
- enum iavf_fc_mode requested_mode; /* FC mode requested by caller */
-};
-
-#define IAVF_MAX_TRAFFIC_CLASS 8
#define IAVF_MAX_USER_PRIORITY 8
-#define IAVF_DCBX_MAX_APPS 32
-#define IAVF_LLDPDU_SIZE 1500
#define IAVF_TLV_STATUS_OPER 0x1
#define IAVF_TLV_STATUS_SYNC 0x2
#define IAVF_TLV_STATUS_ERR 0x4
#define IAVF_CEE_APP_SEL_ETHTYPE 0x0
#define IAVF_CEE_APP_SEL_TCPIP 0x1
-/* CEE or IEEE 802.1Qaz ETS Configuration data */
-struct iavf_dcb_ets_config {
- u8 willing;
- u8 cbs;
- u8 maxtcs;
- u8 prioritytable[IAVF_MAX_TRAFFIC_CLASS];
- u8 tcbwtable[IAVF_MAX_TRAFFIC_CLASS];
- u8 tsatable[IAVF_MAX_TRAFFIC_CLASS];
-};
-
-/* CEE or IEEE 802.1Qaz PFC Configuration data */
-struct iavf_dcb_pfc_config {
- u8 willing;
- u8 mbc;
- u8 pfccap;
- u8 pfcenable;
-};
-
-/* CEE or IEEE 802.1Qaz Application Priority data */
-struct iavf_dcb_app_priority_table {
- u8 priority;
- u8 selector;
- u16 protocolid;
-};
-
-struct iavf_dcbx_config {
- u8 dcbx_mode;
-#define IAVF_DCBX_MODE_CEE 0x1
-#define IAVF_DCBX_MODE_IEEE 0x2
- u8 app_mode;
-#define IAVF_DCBX_APPS_NON_WILLING 0x1
- u32 numapps;
- u32 tlv_status; /* CEE mode TLV status */
- struct iavf_dcb_ets_config etscfg;
- struct iavf_dcb_ets_config etsrec;
- struct iavf_dcb_pfc_config pfc;
- struct iavf_dcb_app_priority_table app[IAVF_DCBX_MAX_APPS];
-};
-
/* Port hardware description */
struct iavf_hw {
u8 *hw_addr;
void *back;
/* subsystem structs */
- struct iavf_phy_info phy;
struct iavf_mac_info mac;
struct iavf_bus_info bus;
- struct iavf_nvm_info nvm;
- struct iavf_fc_info fc;
/* pci info */
u16 device_id;
u16 subsystem_device_id;
u16 subsystem_vendor_id;
u8 revision_id;
- u8 port;
bool adapter_stopped;
/* capabilities for entire device and PCI func */
struct iavf_hw_capabilities dev_caps;
- struct iavf_hw_capabilities func_caps;
-
- /* Flow Director shared filter space */
- u16 fdir_shared_filter_count;
-
- /* device profile info */
- u8 pf_id;
- u16 main_vsi_seid;
-
- /* for multi-function MACs */
- u16 partition_id;
- u16 num_partitions;
- u16 num_ports;
-
- /* Closest numa node to the device */
- u16 numa_node;
/* Admin Queue info */
struct iavf_adminq_info aq;
- /* state of nvm update process */
- enum iavf_nvmupd_state nvmupd_state;
- struct iavf_aq_desc nvm_wb_desc;
- struct iavf_aq_desc nvm_aq_event_desc;
- struct iavf_virt_mem nvm_buff;
- bool nvm_release_on_done;
- u16 nvm_wait_opcode;
-
- /* LLDP/DCBX Status */
- u16 dcbx_status;
-
- /* DCBX info */
- struct iavf_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
- struct iavf_dcbx_config remote_dcbx_config; /* Peer Cfg */
- struct iavf_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
-
/* WoL and proxy support */
u16 num_wol_proxy_filters;
u16 wol_proxy_vsi_seid;
#define IAVF_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1)
#define IAVF_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2)
#define IAVF_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
+#define IAVF_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4)
u64 flags;
- /* Used in set switch config AQ command */
- u16 switch_tag;
- u16 first_tag;
- u16 second_tag;
+ /* NVMUpdate features */
+ struct iavf_nvmupd_features nvmupd_features;
/* debug mask */
u32 debug_mask;
char err_str[16];
};
-STATIC INLINE bool iavf_is_vf(struct iavf_hw *hw)
-{
- return (hw->mac.type == IAVF_MAC_VF ||
- hw->mac.type == IAVF_MAC_X722_VF);
-}
-
struct iavf_driver_version {
u8 major_version;
u8 minor_version;
IAVF_TX_CTX_DESC_SWPE = 0x40
};
-#define IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT 30
-#define IAVF_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
- IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT)
-
-#define IAVF_TXD_CTX_QW1_MSS_SHIFT 50
-#define IAVF_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
- IAVF_TXD_CTX_QW1_MSS_SHIFT)
-
-#define IAVF_TXD_CTX_QW1_VSI_SHIFT 50
-#define IAVF_TXD_CTX_QW1_VSI_MASK (0x1FFULL << IAVF_TXD_CTX_QW1_VSI_SHIFT)
-
-#define IAVF_TXD_CTX_QW0_EXT_IP_SHIFT 0
-#define IAVF_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
- IAVF_TXD_CTX_QW0_EXT_IP_SHIFT)
-
-enum iavf_tx_ctx_desc_eipt_offload {
- IAVF_TX_CTX_EXT_IP_NONE = 0x0,
- IAVF_TX_CTX_EXT_IP_IPV6 = 0x1,
- IAVF_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
- IAVF_TX_CTX_EXT_IP_IPV4 = 0x3
-};
-
-#define IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
-#define IAVF_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
- IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
-
-#define IAVF_TXD_CTX_QW0_NATT_SHIFT 9
-#define IAVF_TXD_CTX_QW0_NATT_MASK (0x3ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
-
-#define IAVF_TXD_CTX_UDP_TUNNELING BIT_ULL(IAVF_TXD_CTX_QW0_NATT_SHIFT)
-#define IAVF_TXD_CTX_GRE_TUNNELING (0x2ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
-
-#define IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
-#define IAVF_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT)
-
-#define IAVF_TXD_CTX_EIP_NOINC_IPID_CONST IAVF_TXD_CTX_QW0_EIP_NOINC_MASK
-
-#define IAVF_TXD_CTX_QW0_NATLEN_SHIFT 12
-#define IAVF_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
- IAVF_TXD_CTX_QW0_NATLEN_SHIFT)
-
-#define IAVF_TXD_CTX_QW0_DECTTL_SHIFT 19
-#define IAVF_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
- IAVF_TXD_CTX_QW0_DECTTL_SHIFT)
-
-#define IAVF_TXD_CTX_QW0_L4T_CS_SHIFT 23
-#define IAVF_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(IAVF_TXD_CTX_QW0_L4T_CS_SHIFT)
struct iavf_nop_desc {
__le64 rsvd;
__le64 dtype_cmd;
IAVF_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */
};
-struct iavf_filter_program_desc {
- __le32 qindex_flex_ptype_vsi;
- __le32 rsvd;
- __le32 dtype_cmd_cntindex;
- __le32 fd_id;
-};
-#define IAVF_TXD_FLTR_QW0_QINDEX_SHIFT 0
-#define IAVF_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
- IAVF_TXD_FLTR_QW0_QINDEX_SHIFT)
-#define IAVF_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
-#define IAVF_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
- IAVF_TXD_FLTR_QW0_FLEXOFF_SHIFT)
-#define IAVF_TXD_FLTR_QW0_PCTYPE_SHIFT 17
-#define IAVF_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
- IAVF_TXD_FLTR_QW0_PCTYPE_SHIFT)
-
/* Packet Classifier Types for filters */
enum iavf_filter_pctype {
/* Note: Values 0-28 are reserved for future use.
IAVF_FILTER_PCTYPE_L2_PAYLOAD = 63,
};
-enum iavf_filter_program_desc_dest {
- IAVF_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
- IAVF_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
- IAVF_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
-};
-
-enum iavf_filter_program_desc_fd_status {
- IAVF_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
- IAVF_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
- IAVF_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
- IAVF_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
-};
-
-#define IAVF_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
-#define IAVF_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
- IAVF_TXD_FLTR_QW0_DEST_VSI_SHIFT)
-
#define IAVF_TXD_FLTR_QW1_DTYPE_SHIFT 0
#define IAVF_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_FLTR_QW1_DTYPE_SHIFT)
-#define IAVF_TXD_FLTR_QW1_CMD_SHIFT 4
-#define IAVF_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
+#define IAVF_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
IAVF_TXD_FLTR_QW1_CMD_SHIFT)
+#define IAVF_TXD_FLTR_QW1_ATR_MASK BIT_ULL(IAVF_TXD_FLTR_QW1_ATR_SHIFT)
-#define IAVF_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + IAVF_TXD_FLTR_QW1_CMD_SHIFT)
-#define IAVF_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << IAVF_TXD_FLTR_QW1_PCMD_SHIFT)
-enum iavf_filter_program_desc_pcmd {
- IAVF_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
- IAVF_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
+#define IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT 30
+#define IAVF_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
+ IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT)
+
+#define IAVF_TXD_CTX_QW1_MSS_SHIFT 50
+#define IAVF_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
+ IAVF_TXD_CTX_QW1_MSS_SHIFT)
+
+#define IAVF_TXD_CTX_QW1_VSI_SHIFT 50
+#define IAVF_TXD_CTX_QW1_VSI_MASK (0x1FFULL << IAVF_TXD_CTX_QW1_VSI_SHIFT)
+
+#define IAVF_TXD_CTX_QW0_EXT_IP_SHIFT 0
+#define IAVF_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
+ IAVF_TXD_CTX_QW0_EXT_IP_SHIFT)
+
+enum iavf_tx_ctx_desc_eipt_offload {
+ IAVF_TX_CTX_EXT_IP_NONE = 0x0,
+ IAVF_TX_CTX_EXT_IP_IPV6 = 0x1,
+ IAVF_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
+ IAVF_TX_CTX_EXT_IP_IPV4 = 0x3
};
-#define IAVF_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + IAVF_TXD_FLTR_QW1_CMD_SHIFT)
-#define IAVF_TXD_FLTR_QW1_DEST_MASK (0x3ULL << IAVF_TXD_FLTR_QW1_DEST_SHIFT)
+#define IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
+#define IAVF_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
+ IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
-#define IAVF_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + IAVF_TXD_FLTR_QW1_CMD_SHIFT)
-#define IAVF_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(IAVF_TXD_FLTR_QW1_CNT_ENA_SHIFT)
+#define IAVF_TXD_CTX_QW0_NATT_SHIFT 9
+#define IAVF_TXD_CTX_QW0_NATT_MASK (0x3ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
-#define IAVF_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
- IAVF_TXD_FLTR_QW1_CMD_SHIFT)
-#define IAVF_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
- IAVF_TXD_FLTR_QW1_FD_STATUS_SHIFT)
+#define IAVF_TXD_CTX_UDP_TUNNELING BIT_ULL(IAVF_TXD_CTX_QW0_NATT_SHIFT)
+#define IAVF_TXD_CTX_GRE_TUNNELING (0x2ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
-#define IAVF_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
- IAVF_TXD_FLTR_QW1_CMD_SHIFT)
-#define IAVF_TXD_FLTR_QW1_ATR_MASK BIT_ULL(IAVF_TXD_FLTR_QW1_ATR_SHIFT)
+#define IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
+#define IAVF_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT)
-#define IAVF_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
-#define IAVF_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
- IAVF_TXD_FLTR_QW1_CNTINDEX_SHIFT)
-
-enum iavf_filter_type {
- IAVF_FLOW_DIRECTOR_FLTR = 0,
- IAVF_PE_QUAD_HASH_FLTR = 1,
- IAVF_ETHERTYPE_FLTR,
- IAVF_FCOE_CTX_FLTR,
- IAVF_MAC_VLAN_FLTR,
- IAVF_HASH_FLTR
-};
+#define IAVF_TXD_CTX_EIP_NOINC_IPID_CONST IAVF_TXD_CTX_QW0_EIP_NOINC_MASK
-struct iavf_vsi_context {
- u16 seid;
- u16 uplink_seid;
- u16 vsi_number;
- u16 vsis_allocated;
- u16 vsis_unallocated;
- u16 flags;
- u8 pf_num;
- u8 vf_num;
- u8 connection_type;
- struct iavf_aqc_vsi_properties_data info;
-};
+#define IAVF_TXD_CTX_QW0_NATLEN_SHIFT 12
+#define IAVF_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
+ IAVF_TXD_CTX_QW0_NATLEN_SHIFT)
-struct iavf_veb_context {
- u16 seid;
- u16 uplink_seid;
- u16 veb_number;
- u16 vebs_allocated;
- u16 vebs_unallocated;
- u16 flags;
- struct iavf_aqc_get_veb_parameters_completion info;
-};
+#define IAVF_TXD_CTX_QW0_DECTTL_SHIFT 19
+#define IAVF_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
+ IAVF_TXD_CTX_QW0_DECTTL_SHIFT)
+
+#define IAVF_TXD_CTX_QW0_L4T_CS_SHIFT 23
+#define IAVF_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(IAVF_TXD_CTX_QW0_L4T_CS_SHIFT)
/* Statistics collected by each port, VSI, VEB, and S-channel */
struct iavf_eth_stats {
u64 tx_discards; /* tdpc */
u64 tx_errors; /* tepc */
};
-
-/* Statistics collected per VEB per TC */
-struct iavf_veb_tc_stats {
- u64 tc_rx_packets[IAVF_MAX_TRAFFIC_CLASS];
- u64 tc_rx_bytes[IAVF_MAX_TRAFFIC_CLASS];
- u64 tc_tx_packets[IAVF_MAX_TRAFFIC_CLASS];
- u64 tc_tx_bytes[IAVF_MAX_TRAFFIC_CLASS];
-};
-
-/* Statistics collected per function for FCoE */
-struct iavf_fcoe_stats {
- u64 rx_fcoe_packets; /* fcoeprc */
- u64 rx_fcoe_dwords; /* focedwrc */
- u64 rx_fcoe_dropped; /* fcoerpdc */
- u64 tx_fcoe_packets; /* fcoeptc */
- u64 tx_fcoe_dwords; /* focedwtc */
- u64 fcoe_bad_fccrc; /* fcoecrc */
- u64 fcoe_last_error; /* fcoelast */
- u64 fcoe_ddp_count; /* fcoeddpc */
-};
-
-/* offset to per function FCoE statistics block */
-#define IAVF_FCOE_VF_STAT_OFFSET 0
-#define IAVF_FCOE_PF_STAT_OFFSET 128
-#define IAVF_FCOE_STAT_MAX (IAVF_FCOE_PF_STAT_OFFSET + IAVF_MAX_PF)
-
-/* Statistics collected by the MAC */
-struct iavf_hw_port_stats {
- /* eth stats collected by the port */
- struct iavf_eth_stats eth;
-
- /* additional port specific stats */
- u64 tx_dropped_link_down; /* tdold */
- u64 crc_errors; /* crcerrs */
- u64 illegal_bytes; /* illerrc */
- u64 error_bytes; /* errbc */
- u64 mac_local_faults; /* mlfc */
- u64 mac_remote_faults; /* mrfc */
- u64 rx_length_errors; /* rlec */
- u64 link_xon_rx; /* lxonrxc */
- u64 link_xoff_rx; /* lxoffrxc */
- u64 priority_xon_rx[8]; /* pxonrxc[8] */
- u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
- u64 link_xon_tx; /* lxontxc */
- u64 link_xoff_tx; /* lxofftxc */
- u64 priority_xon_tx[8]; /* pxontxc[8] */
- u64 priority_xoff_tx[8]; /* pxofftxc[8] */
- u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
- u64 rx_size_64; /* prc64 */
- u64 rx_size_127; /* prc127 */
- u64 rx_size_255; /* prc255 */
- u64 rx_size_511; /* prc511 */
- u64 rx_size_1023; /* prc1023 */
- u64 rx_size_1522; /* prc1522 */
- u64 rx_size_big; /* prc9522 */
- u64 rx_undersize; /* ruc */
- u64 rx_fragments; /* rfc */
- u64 rx_oversize; /* roc */
- u64 rx_jabber; /* rjc */
- u64 tx_size_64; /* ptc64 */
- u64 tx_size_127; /* ptc127 */
- u64 tx_size_255; /* ptc255 */
- u64 tx_size_511; /* ptc511 */
- u64 tx_size_1023; /* ptc1023 */
- u64 tx_size_1522; /* ptc1522 */
- u64 tx_size_big; /* ptc9522 */
- u64 mac_short_packet_dropped; /* mspdc */
- u64 checksum_error; /* xec */
- /* flow director stats */
- u64 fd_atr_match;
- u64 fd_sb_match;
- u64 fd_atr_tunnel_match;
- u32 fd_atr_status;
- u32 fd_sb_status;
- /* EEE LPI */
- u32 tx_lpi_status;
- u32 rx_lpi_status;
- u64 tx_lpi_count; /* etlpic */
- u64 rx_lpi_count; /* erlpic */
-};
-
-/* Checksum and Shadow RAM pointers */
-#define IAVF_SR_NVM_CONTROL_WORD 0x00
#define IAVF_SR_PCIE_ANALOG_CONFIG_PTR 0x03
#define IAVF_SR_PHY_ANALOG_CONFIG_PTR 0x04
#define IAVF_SR_OPTION_ROM_PTR 0x05
#define IAVF_SR_PE_IMAGE_PTR 0x0C
#define IAVF_SR_CSR_PROTECTED_LIST_PTR 0x0D
#define IAVF_SR_MNG_CONFIG_PTR 0x0E
-#define IAVF_EMP_MODULE_PTR 0x0F
-#define IAVF_SR_EMP_MODULE_PTR 0x48
#define IAVF_SR_PBA_FLAGS 0x15
#define IAVF_SR_PBA_BLOCK_PTR 0x16
#define IAVF_SR_BOOT_CONFIG_PTR 0x17
-#define IAVF_NVM_OEM_VER_OFF 0x83
-#define IAVF_SR_NVM_DEV_STARTER_VERSION 0x18
-#define IAVF_SR_NVM_WAKE_ON_LAN 0x19
-#define IAVF_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
#define IAVF_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28
#define IAVF_SR_NVM_MAP_VERSION 0x29
#define IAVF_SR_NVM_IMAGE_VERSION 0x2A
#define IAVF_SR_NVM_STRUCTURE_VERSION 0x2B
-#define IAVF_SR_NVM_EETRACK_LO 0x2D
-#define IAVF_SR_NVM_EETRACK_HI 0x2E
-#define IAVF_SR_VPD_PTR 0x2F
#define IAVF_SR_PXE_SETUP_PTR 0x30
#define IAVF_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31
#define IAVF_SR_NVM_ORIGINAL_EETRACK_LO 0x34
#define IAVF_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
#define IAVF_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
#define IAVF_SR_PHY_ACTIVITY_LIST_PTR 0x3D
-#define IAVF_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
-#define IAVF_SR_SW_CHECKSUM_WORD 0x3F
#define IAVF_SR_1ST_FREE_PROVISION_AREA_PTR 0x40
#define IAVF_SR_4TH_FREE_PROVISION_AREA_PTR 0x42
#define IAVF_SR_3RD_FREE_PROVISION_AREA_PTR 0x44
#define IAVF_SR_FEATURE_CONFIGURATION_PTR 0x49
#define IAVF_SR_CONFIGURATION_METADATA_PTR 0x4D
#define IAVF_SR_IMMEDIATE_VALUES_PTR 0x4E
-
-/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
-#define IAVF_SR_VPD_MODULE_MAX_SIZE 1024
-#define IAVF_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
-#define IAVF_SR_CONTROL_WORD_1_SHIFT 0x06
-#define IAVF_SR_CONTROL_WORD_1_MASK (0x03 << IAVF_SR_CONTROL_WORD_1_SHIFT)
-#define IAVF_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5)
-#define IAVF_SR_NVM_MAP_STRUCTURE_TYPE BIT(12)
-#define IAVF_PTR_TYPE BIT(15)
-
-/* Shadow RAM related */
-#define IAVF_SR_SECTOR_SIZE_IN_WORDS 0x800
+#define IAVF_SR_OCP_CFG_WORD0 0x2B
+#define IAVF_SR_OCP_ENABLED BIT(15)
#define IAVF_SR_BUF_ALIGNMENT 4096
-#define IAVF_SR_WORDS_IN_1KB 512
-/* Checksum should be calculated such that after adding all the words,
- * including the checksum word itself, the sum should be 0xBABA.
- */
-#define IAVF_SR_SW_CHECKSUM_BASE 0xBABA
-
-#define IAVF_SRRD_SRCTL_ATTEMPTS 100000
-
-/* FCoE Tx context descriptor - Use the iavf_tx_context_desc struct */
-
-enum i40E_fcoe_tx_ctx_desc_cmd_bits {
- IAVF_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00, /* 4 BITS */
- IAVF_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01, /* 4 BITS */
- IAVF_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05, /* 4 BITS */
- IAVF_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02, /* 4 BITS */
- IAVF_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06, /* 4 BITS */
- IAVF_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03, /* 4 BITS */
- IAVF_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07, /* 4 BITS */
- IAVF_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08, /* 4 BITS */
- IAVF_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09, /* 4 BITS */
- IAVF_FCOE_TX_CTX_DESC_RELOFF = 0x10,
- IAVF_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
- IAVF_FCOE_TX_CTX_DESC_DIFENA = 0x40,
- IAVF_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
-};
-/* FCoE DIF/DIX Context descriptor */
-struct iavf_fcoe_difdix_context_desc {
- __le64 flags_buff0_buff1_ref;
- __le64 difapp_msk_bias;
-};
-
-#define IAVF_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT 0
-#define IAVF_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK (0xFFFULL << \
- IAVF_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
-
-enum iavf_fcoe_difdix_ctx_desc_flags_bits {
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_RSVD = 0x0000,
- /* 1 BIT */
- IAVF_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK = 0x0000,
- /* 1 BIT */
- IAVF_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK = 0x0004,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE = 0x0000,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY = 0x0008,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG = 0x0010,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG = 0x0018,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST = 0x0000,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK = 0x0020,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG = 0x0040,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD = 0x0060,
- /* 1 BIT */
- IAVF_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM = 0x0000,
- /* 1 BIT */
- IAVF_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC = 0x0080,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG = 0x0000,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF = 0x0100,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD = 0x0200,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS = 0x0300,
- /* 1 BIT */
- IAVF_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG = 0x0000,
- /* 1 BIT */
- IAVF_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG = 0x0400,
- /* 1 BIT */
- IAVF_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B = 0x0000,
- /* 1 BIT */
- IAVF_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K = 0x0800
-};
-
-#define IAVF_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT 12
-#define IAVF_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK (0x3FFULL << \
- IAVF_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
-
-#define IAVF_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT 22
-#define IAVF_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK (0x3FFULL << \
- IAVF_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
-
-#define IAVF_FCOE_DIFDIX_CTX_QW0_REF_SHIFT 32
-#define IAVF_FCOE_DIFDIX_CTX_QW0_REF_MASK (0xFFFFFFFFULL << \
- IAVF_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
-
-#define IAVF_FCOE_DIFDIX_CTX_QW1_APP_SHIFT 0
-#define IAVF_FCOE_DIFDIX_CTX_QW1_APP_MASK (0xFFFFULL << \
- IAVF_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
-
-#define IAVF_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT 16
-#define IAVF_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK (0xFFFFULL << \
- IAVF_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
-
-#define IAVF_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
-#define IAVF_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK (0xFFFFFFFFULL << \
- IAVF_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
-
-/* FCoE DIF/DIX Buffers descriptor */
-struct iavf_fcoe_difdix_buffers_desc {
- __le64 buff_addr0;
- __le64 buff_addr1;
-};
-
-/* FCoE DDP Context descriptor */
-struct iavf_fcoe_ddp_context_desc {
- __le64 rsvd;
- __le64 type_cmd_foff_lsize;
-};
-#define IAVF_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
-#define IAVF_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
- IAVF_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
-
-#define IAVF_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
-#define IAVF_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
- IAVF_FCOE_DDP_CTX_QW1_CMD_SHIFT)
-
-enum iavf_fcoe_ddp_ctx_desc_cmd_bits {
- IAVF_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00, /* 2 BITS */
- IAVF_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01, /* 2 BITS */
- IAVF_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02, /* 2 BITS */
- IAVF_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03, /* 2 BITS */
- IAVF_FCOE_DDP_CTX_DESC_DIFENA = 0x04, /* 1 BIT */
- IAVF_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08, /* 1 BIT */
-};
-
-#define IAVF_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
-#define IAVF_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
- IAVF_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
-
-#define IAVF_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
-#define IAVF_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
- IAVF_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
-
-/* FCoE DDP/DWO Queue Context descriptor */
-struct iavf_fcoe_queue_context_desc {
- __le64 dmaindx_fbase; /* 0:11 DMAINDX, 12:63 FBASE */
- __le64 flen_tph; /* 0:12 FLEN, 13:15 TPH */
-};
-
-#define IAVF_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
-#define IAVF_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
- IAVF_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
-
-#define IAVF_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
-#define IAVF_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
- IAVF_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
-
-#define IAVF_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
-#define IAVF_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
- IAVF_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
-
-#define IAVF_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
-#define IAVF_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
- IAVF_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
-
-enum iavf_fcoe_queue_ctx_desc_tph_bits {
- IAVF_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
- IAVF_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
-};
-
-#define IAVF_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
-#define IAVF_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
- IAVF_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
-
-/* FCoE DDP/DWO Filter Context descriptor */
-struct iavf_fcoe_filter_context_desc {
- __le32 param;
- __le16 seqn;
-
- /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
- __le16 rsvd_dmaindx;
-
- /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
- __le64 flags_rsvd_lanq;
-};
-
-#define IAVF_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
-#define IAVF_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
- IAVF_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
-
-enum iavf_fcoe_filter_ctx_desc_flags_bits {
- IAVF_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
- IAVF_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
- IAVF_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
- IAVF_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
- IAVF_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
- IAVF_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
-};
-
-#define IAVF_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
-#define IAVF_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
- IAVF_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
-
-#define IAVF_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
-#define IAVF_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
- IAVF_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
-
-#define IAVF_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
-#define IAVF_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
- IAVF_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
-
-enum iavf_switch_element_types {
- IAVF_SWITCH_ELEMENT_TYPE_MAC = 1,
- IAVF_SWITCH_ELEMENT_TYPE_PF = 2,
- IAVF_SWITCH_ELEMENT_TYPE_VF = 3,
- IAVF_SWITCH_ELEMENT_TYPE_EMP = 4,
- IAVF_SWITCH_ELEMENT_TYPE_BMC = 6,
- IAVF_SWITCH_ELEMENT_TYPE_PE = 16,
- IAVF_SWITCH_ELEMENT_TYPE_VEB = 17,
- IAVF_SWITCH_ELEMENT_TYPE_PA = 18,
- IAVF_SWITCH_ELEMENT_TYPE_VSI = 19,
-};
-
-/* Supported EtherType filters */
-enum iavf_ether_type_index {
- IAVF_ETHER_TYPE_1588 = 0,
- IAVF_ETHER_TYPE_FIP = 1,
- IAVF_ETHER_TYPE_OUI_EXTENDED = 2,
- IAVF_ETHER_TYPE_MAC_CONTROL = 3,
- IAVF_ETHER_TYPE_LLDP = 4,
- IAVF_ETHER_TYPE_EVB_PROTOCOL1 = 5,
- IAVF_ETHER_TYPE_EVB_PROTOCOL2 = 6,
- IAVF_ETHER_TYPE_QCN_CNM = 7,
- IAVF_ETHER_TYPE_8021X = 8,
- IAVF_ETHER_TYPE_ARP = 9,
- IAVF_ETHER_TYPE_RSV1 = 10,
- IAVF_ETHER_TYPE_RSV2 = 11,
-};
-
-/* Filter context base size is 1K */
-#define IAVF_HASH_FILTER_BASE_SIZE 1024
-/* Supported Hash filter values */
-enum iavf_hash_filter_size {
- IAVF_HASH_FILTER_SIZE_1K = 0,
- IAVF_HASH_FILTER_SIZE_2K = 1,
- IAVF_HASH_FILTER_SIZE_4K = 2,
- IAVF_HASH_FILTER_SIZE_8K = 3,
- IAVF_HASH_FILTER_SIZE_16K = 4,
- IAVF_HASH_FILTER_SIZE_32K = 5,
- IAVF_HASH_FILTER_SIZE_64K = 6,
- IAVF_HASH_FILTER_SIZE_128K = 7,
- IAVF_HASH_FILTER_SIZE_256K = 8,
- IAVF_HASH_FILTER_SIZE_512K = 9,
- IAVF_HASH_FILTER_SIZE_1M = 10,
-};
-
-/* DMA context base size is 0.5K */
-#define IAVF_DMA_CNTX_BASE_SIZE 512
-/* Supported DMA context values */
-enum iavf_dma_cntx_size {
- IAVF_DMA_CNTX_SIZE_512 = 0,
- IAVF_DMA_CNTX_SIZE_1K = 1,
- IAVF_DMA_CNTX_SIZE_2K = 2,
- IAVF_DMA_CNTX_SIZE_4K = 3,
- IAVF_DMA_CNTX_SIZE_8K = 4,
- IAVF_DMA_CNTX_SIZE_16K = 5,
- IAVF_DMA_CNTX_SIZE_32K = 6,
- IAVF_DMA_CNTX_SIZE_64K = 7,
- IAVF_DMA_CNTX_SIZE_128K = 8,
- IAVF_DMA_CNTX_SIZE_256K = 9,
-};
-
-/* Supported Hash look up table (LUT) sizes */
-enum iavf_hash_lut_size {
- IAVF_HASH_LUT_SIZE_128 = 0,
- IAVF_HASH_LUT_SIZE_512 = 1,
-};
-
-/* Structure to hold a per PF filter control settings */
-struct iavf_filter_control_settings {
- /* number of PE Quad Hash filter buckets */
- enum iavf_hash_filter_size pe_filt_num;
- /* number of PE Quad Hash contexts */
- enum iavf_dma_cntx_size pe_cntx_num;
- /* number of FCoE filter buckets */
- enum iavf_hash_filter_size fcoe_filt_num;
- /* number of FCoE DDP contexts */
- enum iavf_dma_cntx_size fcoe_cntx_num;
- /* size of the Hash LUT */
- enum iavf_hash_lut_size hash_lut_size;
- /* enable FDIR filters for PF and its VFs */
- bool enable_fdir;
- /* enable Ethertype filters for PF and its VFs */
- bool enable_ethtype;
- /* enable MAC/VLAN filters for PF and its VFs */
- bool enable_macvlan;
-};
-
-/* Structure to hold device level control filter counts */
-struct iavf_control_filter_stats {
- u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
- u16 etype_used; /* Used perfect EtherType filters */
- u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
- u16 etype_free; /* Un-used perfect EtherType filters */
-};
-
-enum iavf_reset_type {
- IAVF_RESET_POR = 0,
- IAVF_RESET_CORER = 1,
- IAVF_RESET_GLOBR = 2,
- IAVF_RESET_EMPR = 3,
-};
-
-/* IEEE 802.1AB LLDP Agent Variables from NVM */
-#define IAVF_NVM_LLDP_CFG_PTR 0x06
-#define IAVF_SR_LLDP_CFG_PTR 0x31
struct iavf_lldp_variables {
u16 length;
u16 adminstatus;
#define IAVF_ALT_BW_RELATIVE_MASK 0x40000000
#define IAVF_ALT_BW_VALID_MASK 0x80000000
-/* RSS Hash Table Size */
-#define IAVF_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
-
-/* INPUT SET MASK for RSS, flow director, and flexible payload */
-#define IAVF_L3_SRC_SHIFT 47
-#define IAVF_L3_SRC_MASK (0x3ULL << IAVF_L3_SRC_SHIFT)
-#define IAVF_L3_V6_SRC_SHIFT 43
-#define IAVF_L3_V6_SRC_MASK (0xFFULL << IAVF_L3_V6_SRC_SHIFT)
-#define IAVF_L3_DST_SHIFT 35
-#define IAVF_L3_DST_MASK (0x3ULL << IAVF_L3_DST_SHIFT)
-#define IAVF_L3_V6_DST_SHIFT 35
-#define IAVF_L3_V6_DST_MASK (0xFFULL << IAVF_L3_V6_DST_SHIFT)
-#define IAVF_L4_SRC_SHIFT 34
-#define IAVF_L4_SRC_MASK (0x1ULL << IAVF_L4_SRC_SHIFT)
-#define IAVF_L4_DST_SHIFT 33
-#define IAVF_L4_DST_MASK (0x1ULL << IAVF_L4_DST_SHIFT)
-#define IAVF_VERIFY_TAG_SHIFT 31
-#define IAVF_VERIFY_TAG_MASK (0x3ULL << IAVF_VERIFY_TAG_SHIFT)
-
-#define IAVF_FLEX_50_SHIFT 13
-#define IAVF_FLEX_50_MASK (0x1ULL << IAVF_FLEX_50_SHIFT)
-#define IAVF_FLEX_51_SHIFT 12
-#define IAVF_FLEX_51_MASK (0x1ULL << IAVF_FLEX_51_SHIFT)
-#define IAVF_FLEX_52_SHIFT 11
-#define IAVF_FLEX_52_MASK (0x1ULL << IAVF_FLEX_52_SHIFT)
-#define IAVF_FLEX_53_SHIFT 10
-#define IAVF_FLEX_53_MASK (0x1ULL << IAVF_FLEX_53_SHIFT)
-#define IAVF_FLEX_54_SHIFT 9
-#define IAVF_FLEX_54_MASK (0x1ULL << IAVF_FLEX_54_SHIFT)
-#define IAVF_FLEX_55_SHIFT 8
-#define IAVF_FLEX_55_MASK (0x1ULL << IAVF_FLEX_55_SHIFT)
-#define IAVF_FLEX_56_SHIFT 7
-#define IAVF_FLEX_56_MASK (0x1ULL << IAVF_FLEX_56_SHIFT)
-#define IAVF_FLEX_57_SHIFT 6
-#define IAVF_FLEX_57_MASK (0x1ULL << IAVF_FLEX_57_SHIFT)
-
-/* Version format for Dynamic Device Personalization(DDP) */
-struct iavf_ddp_version {
- u8 major;
- u8 minor;
- u8 update;
- u8 draft;
-};
-
-#define IAVF_DDP_NAME_SIZE 32
-
-/* Package header */
-struct iavf_package_header {
- struct iavf_ddp_version version;
- u32 segment_count;
- u32 segment_offset[1];
-};
-
-/* Generic segment header */
-struct iavf_generic_seg_header {
-#define SEGMENT_TYPE_METADATA 0x00000001
-#define SEGMENT_TYPE_NOTES 0x00000002
-#define SEGMENT_TYPE_IAVF 0x00000011
-#define SEGMENT_TYPE_X722 0x00000012
- u32 type;
- struct iavf_ddp_version version;
- u32 size;
- char name[IAVF_DDP_NAME_SIZE];
-};
-
-struct iavf_metadata_segment {
- struct iavf_generic_seg_header header;
- struct iavf_ddp_version version;
#define IAVF_DDP_TRACKID_RDONLY 0
#define IAVF_DDP_TRACKID_INVALID 0xFFFFFFFF
- u32 track_id;
- char name[IAVF_DDP_NAME_SIZE];
-};
-
-struct iavf_device_id_entry {
- u32 vendor_dev_id;
- u32 sub_vendor_dev_id;
-};
-
-struct iavf_profile_segment {
- struct iavf_generic_seg_header header;
- struct iavf_ddp_version version;
- char name[IAVF_DDP_NAME_SIZE];
- u32 device_table_count;
- struct iavf_device_id_entry device_table[1];
-};
-
-struct iavf_section_table {
- u32 section_count;
- u32 section_offset[1];
-};
-
-struct iavf_profile_section_header {
- u16 tbl_size;
- u16 data_end;
- struct {
-#define SECTION_TYPE_INFO 0x00000010
-#define SECTION_TYPE_MMIO 0x00000800
#define SECTION_TYPE_RB_MMIO 0x00001800
-#define SECTION_TYPE_AQ 0x00000801
#define SECTION_TYPE_RB_AQ 0x00001801
-#define SECTION_TYPE_NOTE 0x80000000
-#define SECTION_TYPE_NAME 0x80000001
#define SECTION_TYPE_PROTO 0x80000002
#define SECTION_TYPE_PCTYPE 0x80000003
#define SECTION_TYPE_PTYPE 0x80000004
- u32 type;
- u32 offset;
- u32 size;
- } section;
-};
-
struct iavf_profile_tlv_section_record {
u8 rtype;
u8 type;
u8 data[1];
};
-struct iavf_profile_info {
- u32 track_id;
- struct iavf_ddp_version version;
- u8 op;
-#define IAVF_DDP_ADD_TRACKID 0x01
-#define IAVF_DDP_REMOVE_TRACKID 0x02
- u8 reserved[7];
- u8 name[IAVF_DDP_NAME_SIZE];
-};
#endif /* _IAVF_TYPE_H_ */
git.droids-corp.org / dpdk.git / commitdiff