#
LIB = librte_pmd_cxgbe.a
-CFLAGS += -I$(SRCDIR)/base/
-CFLAGS += -I$(SRCDIR)
CFLAGS += -O3
CFLAGS += $(WERROR_FLAGS)
#include <rte_rwlock.h>
#include <rte_ethdev.h>
-#include "cxgbe_compat.h"
+#include "../cxgbe_compat.h"
+#include "../cxgbe_ofld.h"
#include "t4_regs_values.h"
-#include "cxgbe_ofld.h"
enum {
MAX_ETH_QSETS = 64, /* # of Ethernet Tx/Rx queue sets */
#ifndef __CHELSIO_COMMON_H
#define __CHELSIO_COMMON_H
-#include "cxgbe_compat.h"
+#include "../cxgbe_compat.h"
#include "t4_hw.h"
#include "t4vf_hw.h"
#include "t4_chip_type.h"
* All rights reserved.
*/
-#include "common.h"
+#include "base/common.h"
#include "clip_tbl.h"
/**
#ifndef _CXGBE_H_
#define _CXGBE_H_
-#include "common.h"
-#include "t4_regs.h"
+#include "base/common.h"
+#include "base/t4_regs.h"
#define CXGBE_MIN_RING_DESC_SIZE 128 /* Min TX/RX descriptor ring size */
#define CXGBE_MAX_RING_DESC_SIZE 4096 /* Max TX/RX descriptor ring size */
/*
*... and the PCI ID Table itself ...
*/
-#include "t4_pci_id_tbl.h"
+#include "base/t4_pci_id_tbl.h"
uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
uint16_t nb_pkts)
* All rights reserved.
*/
#include <rte_net.h>
-#include "common.h"
-#include "t4_tcb.h"
-#include "t4_regs.h"
+
+#include "base/common.h"
+#include "base/t4_tcb.h"
+#include "base/t4_regs.h"
#include "cxgbe_filter.h"
#include "clip_tbl.h"
#include "l2t.h"
#ifndef _CXGBE_FILTER_H_
#define _CXGBE_FILTER_H_
-#include "t4_msg.h"
+#include "base/t4_msg.h"
/*
* Defined bit width of user definable filter tuples
*/
* Copyright(c) 2018 Chelsio Communications.
* All rights reserved.
*/
-#include "common.h"
+#include "base/common.h"
#include "cxgbe_flow.h"
#define __CXGBE_FILL_FS(__v, __m, fs, elem, e) \
#include <rte_dev.h>
#include <rte_kvargs.h>
-#include "common.h"
-#include "t4_regs.h"
-#include "t4_msg.h"
+#include "base/common.h"
+#include "base/t4_regs.h"
+#include "base/t4_msg.h"
#include "cxgbe.h"
#include "clip_tbl.h"
#include "l2t.h"
/*
*... and the PCI ID Table itself ...
*/
-#include "t4_pci_id_tbl.h"
+#include "base/t4_pci_id_tbl.h"
/*
* Get port statistics.
#include <rte_ethdev_pci.h>
#include <rte_malloc.h>
-#include "common.h"
-#include "t4_regs.h"
-#include "t4_msg.h"
+#include "base/common.h"
+#include "base/t4_regs.h"
+#include "base/t4_msg.h"
#include "cxgbe.h"
#include "mps_tcam.h"
* Copyright(c) 2018 Chelsio Communications.
* All rights reserved.
*/
-#include "common.h"
+
+#include "base/common.h"
#include "l2t.h"
/**
#ifndef _CXGBE_L2T_H_
#define _CXGBE_L2T_H_
-#include "t4_msg.h"
+#include "base/t4_msg.h"
enum {
L2T_SIZE = 4096 /* # of L2T entries */
#ifndef _CXGBE_MPSTCAM_H_
#define _CXGBE_MPSTCAM_H_
-#include "common.h"
+#include "base/common.h"
enum {
MPS_ENTRY_UNUSED, /* Keep this first so memset 0 renders
#include <rte_random.h>
#include <rte_dev.h>
-#include "common.h"
-#include "t4_regs.h"
-#include "t4_msg.h"
+#include "base/common.h"
+#include "base/t4_regs.h"
+#include "base/t4_msg.h"
#include "cxgbe.h"
static inline void ship_tx_pkt_coalesce_wr(struct adapter *adap,