]> git.droids-corp.org - dpdk.git/commitdiff
net/cxgbe: use relative paths for includes
authorRahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Wed, 19 Dec 2018 16:28:23 +0000 (21:58 +0530)
committerFerruh Yigit <ferruh.yigit@intel.com>
Fri, 21 Dec 2018 15:22:41 +0000 (16:22 +0100)
The Intel C++ compiler is not able to locate the header files without
relative paths in Windows build. Following errors are seen for these
header files.

C:\> base\common.h(9): error : cannot open source file "cxgbe_compat.h"
        #include "cxgbe_compat.h"
                                 ^
[...]

Fix by explicitly stating header file location using relative paths.
Also, remove automatically including header files for Linux, to keep
it consistent across both OS.

Build Environment:
1. Target OS: Microsoft Windows Server 2016
2. Compiler: Intel C++ Compiler from Intel Parallel Studio XE 2019 [1]
3. Development Tools:
   3.1 Microsoft Visual Studio 2017 Professional
   3.2 Windows Software Development Kit (SDK) v10.0.17763
   3.3 Windows Driver Kit (WDK) v10.0.17763

[1] https://software.intel.com/en-us/parallel-studio-xe

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
16 files changed:
drivers/net/cxgbe/Makefile
drivers/net/cxgbe/base/adapter.h
drivers/net/cxgbe/base/common.h
drivers/net/cxgbe/clip_tbl.c
drivers/net/cxgbe/cxgbe.h
drivers/net/cxgbe/cxgbe_ethdev.c
drivers/net/cxgbe/cxgbe_filter.c
drivers/net/cxgbe/cxgbe_filter.h
drivers/net/cxgbe/cxgbe_flow.c
drivers/net/cxgbe/cxgbe_main.c
drivers/net/cxgbe/cxgbevf_ethdev.c
drivers/net/cxgbe/cxgbevf_main.c
drivers/net/cxgbe/l2t.c
drivers/net/cxgbe/l2t.h
drivers/net/cxgbe/mps_tcam.h
drivers/net/cxgbe/sge.c

index 68466f13ee6dd6b9b4f04d4e49b342a9414c4ac8..d809f4720959f8d252d5d4f93d49110f03b8feeb 100644 (file)
@@ -9,8 +9,6 @@ include $(RTE_SDK)/mk/rte.vars.mk
 #
 LIB = librte_pmd_cxgbe.a
 
-CFLAGS += -I$(SRCDIR)/base/
-CFLAGS += -I$(SRCDIR)
 CFLAGS += -O3
 CFLAGS += $(WERROR_FLAGS)
 
index 47cfc5f5fd715edd3eabed37f165da4e2b04bc11..17ce60d04f91749815a02e4953036bf2b10f9caf 100644 (file)
@@ -14,9 +14,9 @@
 #include <rte_rwlock.h>
 #include <rte_ethdev.h>
 
-#include "cxgbe_compat.h"
+#include "../cxgbe_compat.h"
+#include "../cxgbe_ofld.h"
 #include "t4_regs_values.h"
-#include "cxgbe_ofld.h"
 
 enum {
        MAX_ETH_QSETS = 64,           /* # of Ethernet Tx/Rx queue sets */
index fd20066828261b007bfed64e40c9d44eae9caecb..84311fc952b89641b350d5394c83fab6a093978e 100644 (file)
@@ -6,7 +6,7 @@
 #ifndef __CHELSIO_COMMON_H
 #define __CHELSIO_COMMON_H
 
-#include "cxgbe_compat.h"
+#include "../cxgbe_compat.h"
 #include "t4_hw.h"
 #include "t4vf_hw.h"
 #include "t4_chip_type.h"
index 5e4dc527043b8e438ac0b556aabd44b2975d7d0d..a0ab2a6ac82e8a644a5c19c72d0ceb23f352bc16 100644 (file)
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-#include "common.h"
+#include "base/common.h"
 #include "clip_tbl.h"
 
 /**
index eb58f880243e1f5015e3de3319fbc1b86cd01dfc..5a7490f914c82cdfa7603ed6fe691cca960a4f2f 100644 (file)
@@ -6,8 +6,8 @@
 #ifndef _CXGBE_H_
 #define _CXGBE_H_
 
-#include "common.h"
-#include "t4_regs.h"
+#include "base/common.h"
+#include "base/t4_regs.h"
 
 #define CXGBE_MIN_RING_DESC_SIZE      128  /* Min TX/RX descriptor ring size */
 #define CXGBE_MAX_RING_DESC_SIZE      4096 /* Max TX/RX descriptor ring size */
index b2f83ea37b6d0277ef9cbe29684244c870d61ad8..010a818eb61856109f7503831d3eaa916bd29591 100644 (file)
@@ -57,7 +57,7 @@
 /*
  *... and the PCI ID Table itself ...
  */
-#include "t4_pci_id_tbl.h"
+#include "base/t4_pci_id_tbl.h"
 
 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
                         uint16_t nb_pkts)
index 3a7912e48861f88446583e1c968b7cc4f1d49cff..86a6158fd45e28964d1486b489d242966c304fea 100644 (file)
@@ -3,9 +3,10 @@
  * All rights reserved.
  */
 #include <rte_net.h>
-#include "common.h"
-#include "t4_tcb.h"
-#include "t4_regs.h"
+
+#include "base/common.h"
+#include "base/t4_tcb.h"
+#include "base/t4_regs.h"
 #include "cxgbe_filter.h"
 #include "clip_tbl.h"
 #include "l2t.h"
index b7bcbf56a284b3012b55c10e110617c21e881c5b..2d60777185c60eccebcffd8fa8d3377568cd8da4 100644 (file)
@@ -6,7 +6,7 @@
 #ifndef _CXGBE_FILTER_H_
 #define _CXGBE_FILTER_H_
 
-#include "t4_msg.h"
+#include "base/t4_msg.h"
 /*
  * Defined bit width of user definable filter tuples
  */
index 7b87bdf583a0fe7fd28b211dd6dd20607a79eae5..099499c2b35f93c05b9fe4e3077cbf41a6de9655 100644 (file)
@@ -2,7 +2,7 @@
  * Copyright(c) 2018 Chelsio Communications.
  * All rights reserved.
  */
-#include "common.h"
+#include "base/common.h"
 #include "cxgbe_flow.h"
 
 #define __CXGBE_FILL_FS(__v, __m, fs, elem, e) \
index 5fa6cdd0521d5f9eed636de9a75743aa3a3852fc..fd0707b95580d47d8498959e8097adda33be2f25 100644 (file)
@@ -33,9 +33,9 @@
 #include <rte_dev.h>
 #include <rte_kvargs.h>
 
-#include "common.h"
-#include "t4_regs.h"
-#include "t4_msg.h"
+#include "base/common.h"
+#include "base/t4_regs.h"
+#include "base/t4_msg.h"
 #include "cxgbe.h"
 #include "clip_tbl.h"
 #include "l2t.h"
index a6458d533c2230dd2bc26115041b2f20010e0882..0e93d99e6e4d4feee39e03f424fb317dfae2a840 100644 (file)
@@ -28,7 +28,7 @@
 /*
  *... and the PCI ID Table itself ...
  */
-#include "t4_pci_id_tbl.h"
+#include "base/t4_pci_id_tbl.h"
 
 /*
  * Get port statistics.
index 61bd85193aeddf472ee54a786671fc11decda6f8..f440b43457e8c1c36e5898fed09e212a9829fe6b 100644 (file)
@@ -7,9 +7,9 @@
 #include <rte_ethdev_pci.h>
 #include <rte_malloc.h>
 
-#include "common.h"
-#include "t4_regs.h"
-#include "t4_msg.h"
+#include "base/common.h"
+#include "base/t4_regs.h"
+#include "base/t4_msg.h"
 #include "cxgbe.h"
 #include "mps_tcam.h"
 
index 814188fea2f5f83f0add5c4a3aed270876d1692d..27cdf6f33d82baa3d717425e627b0c1d260257b1 100644 (file)
@@ -2,7 +2,8 @@
  * Copyright(c) 2018 Chelsio Communications.
  * All rights reserved.
  */
-#include "common.h"
+
+#include "base/common.h"
 #include "l2t.h"
 
 /**
index 22a34e388bb66e1182a834dbfc481f6426013227..ee40dc1f684dde0851317b949a1b8c640b03bc7e 100644 (file)
@@ -5,7 +5,7 @@
 #ifndef _CXGBE_L2T_H_
 #define _CXGBE_L2T_H_
 
-#include "t4_msg.h"
+#include "base/t4_msg.h"
 
 enum {
        L2T_SIZE = 4096       /* # of L2T entries */
index c3d6fe0d76838a5860eba5ba8b6e51df57843493..f86bac7bd963c039a94f81e82a97b076034264b0 100644 (file)
@@ -6,7 +6,7 @@
 #ifndef _CXGBE_MPSTCAM_H_
 #define _CXGBE_MPSTCAM_H_
 
-#include "common.h"
+#include "base/common.h"
 
 enum {
        MPS_ENTRY_UNUSED,       /* Keep this first so memset 0 renders
index f9d2d48a0217b623d01f8da55204a1b0b106fef6..bf0afb138e5c9366a6852c6fabf4b2249a0f535d 100644 (file)
@@ -33,9 +33,9 @@
 #include <rte_random.h>
 #include <rte_dev.h>
 
-#include "common.h"
-#include "t4_regs.h"
-#include "t4_msg.h"
+#include "base/common.h"
+#include "base/t4_regs.h"
+#include "base/t4_msg.h"
 #include "cxgbe.h"
 
 static inline void ship_tx_pkt_coalesce_wr(struct adapter *adap,