]> git.droids-corp.org - dpdk.git/commitdiff
crypto/dpaa_sec: enable QI physically
authorGagandeep Singh <g.singh@nxp.com>
Thu, 28 Apr 2022 11:47:24 +0000 (17:17 +0530)
committerAkhil Goyal <gakhil@marvell.com>
Fri, 29 Apr 2022 09:27:35 +0000 (11:27 +0200)
To perform crypto operations on DPAA platform,
QI interface of HW must be enabled.
Earlier DPAA crypto driver was dependent on
kernel for QI enable. Now with this patch
there is no such dependency on kernel.

Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
drivers/crypto/dpaa_sec/dpaa_sec.c
drivers/crypto/dpaa_sec/dpaa_sec.h

index ed12d6663bb52374e47d88dc8b75583da95a5704..23a94d7e41ac82b475824a3706dbc69ae8a459d3 100644 (file)
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  *
  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
- *   Copyright 2017-2021 NXP
+ *   Copyright 2017-2022 NXP
  *
  */
 
@@ -20,6 +20,7 @@
 #endif
 #include <rte_cycles.h>
 #include <rte_dev.h>
+#include <rte_io.h>
 #include <rte_ip.h>
 #include <rte_kvargs.h>
 #include <rte_malloc.h>
@@ -3654,9 +3655,35 @@ dpaa_sec_dev_init(struct rte_cryptodev *cryptodev)
        struct dpaa_sec_qp *qp;
        uint32_t i, flags;
        int ret;
+       void *cmd_map;
+       int map_fd = -1;
 
        PMD_INIT_FUNC_TRACE();
 
+       internals = cryptodev->data->dev_private;
+       map_fd = open("/dev/mem", O_RDWR);
+       if (unlikely(map_fd < 0)) {
+               DPAA_SEC_ERR("Unable to open (/dev/mem)");
+               return map_fd;
+       }
+       internals->sec_hw = mmap(NULL, MAP_SIZE, PROT_READ | PROT_WRITE,
+                           MAP_SHARED, map_fd, SEC_BASE_ADDR);
+       if (internals->sec_hw == MAP_FAILED) {
+               DPAA_SEC_ERR("Memory map failed");
+               close(map_fd);
+               return -EINVAL;
+       }
+       cmd_map = (uint8_t *)internals->sec_hw +
+                 (BLOCK_OFFSET * QI_BLOCK_NUMBER) + CMD_REG;
+       if (!(be32_to_cpu(rte_read32(cmd_map)) & QICTL_DQEN))
+               /* enable QI interface */
+               rte_write32(cpu_to_be32(QICTL_DQEN), cmd_map);
+
+       ret = munmap(internals->sec_hw, MAP_SIZE);
+       if (ret)
+               DPAA_SEC_WARN("munmap failed\n");
+
+       close(map_fd);
        cryptodev->driver_id = dpaa_cryptodev_driver_id;
        cryptodev->dev_ops = &crypto_ops;
 
@@ -3673,7 +3700,6 @@ dpaa_sec_dev_init(struct rte_cryptodev *cryptodev)
                        RTE_CRYPTODEV_FF_OOP_LB_IN_SGL_OUT |
                        RTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT;
 
-       internals = cryptodev->data->dev_private;
        internals->max_nb_queue_pairs = RTE_DPAA_MAX_NB_SEC_QPS;
        internals->max_nb_sessions = RTE_DPAA_SEC_PMD_MAX_NB_SESSIONS;
 
index b3f2258ead0fba436d07bea0dbb87ed1bcbfba3b..8921e3ed89026d2548e97b565d8791be35341f07 100644 (file)
 #define CRYPTODEV_NAME_DPAA_SEC_PMD    crypto_dpaa_sec
 /**< NXP DPAA - SEC PMD device name */
 
+#define SEC_BASE_ADDR          0x1700000
+#define MAP_SIZE               0x100000
+#define BLOCK_OFFSET           0x10000
+#define CMD_REG                        0x4
+#define QICTL_DQEN             0x01
+#define QI_BLOCK_NUMBER                7
 #define MAX_DPAA_CORES         4
 #define NUM_POOL_CHANNELS      4
 #define DPAA_SEC_BURST         7