/* handle eq element */
switch (opcode) {
case EVENT_RING_OPCODE_STAT_QUERY:
- PMD_DRV_LOG(DEBUG, "got statistics completion event %d",
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, "got statistics completion event %d",
sc->stats_comp++);
/* nothing to do with stats comp */
goto next_spqe;
/* SP events: STAT_QUERY and others */
if (status & BNX2X_DEF_SB_IDX) {
/* handle EQ completions */
- PMD_DRV_LOG(DEBUG, "---> EQ INTR <---");
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, "---> EQ INTR <---");
bnx2x_eq_int(sc);
bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
le16toh(sc->def_idx), IGU_INT_NOP, 1);
return 0;
}
- PMD_DRV_LOG(DEBUG, "Interrupt status 0x%04x", status);
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, "Interrupt status 0x%04x", status);
//bnx2x_dump_status_block(sc);
FOR_EACH_ETH_QUEUE(sc, i) {
void
bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val)
{
- PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%02x", offset, val);
- *((volatile uint8_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val;
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x", (unsigned long)offset, val);
+ *((volatile uint8_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;
}
void
bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val)
{
if ((offset % 2) != 0) {
- PMD_DRV_LOG(DEBUG, "Unaligned 16-bit write to 0x%08lx", offset);
+ PMD_DRV_LOG(NOTICE, "Unaligned 16-bit write to 0x%08lx",
+ (unsigned long)offset);
}
- PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%04x", offset, val);
- *((volatile uint16_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val;
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%04x", (unsigned long)offset, val);
+ *((volatile uint16_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;
}
void
bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val)
{
if ((offset % 4) != 0) {
- PMD_DRV_LOG(DEBUG, "Unaligned 32-bit write to 0x%08lx", offset);
+ PMD_DRV_LOG(NOTICE, "Unaligned 32-bit write to 0x%08lx",
+ (unsigned long)offset);
}
- PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%08x", offset, val);
- *((volatile uint32_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val;
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x", (unsigned long)offset, val);
+ *((volatile uint32_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val;
}
uint8_t
{
uint8_t val;
- val = (uint8_t)(*((volatile uint8_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)));
- PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%02x", offset, val);
+ val = (uint8_t)(*((volatile uint8_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)));
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x", (unsigned long)offset, val);
return (val);
}
uint16_t val;
if ((offset % 2) != 0) {
- PMD_DRV_LOG(DEBUG, "Unaligned 16-bit read from 0x%08lx", offset);
+ PMD_DRV_LOG(NOTICE, "Unaligned 16-bit read from 0x%08lx",
+ (unsigned long)offset);
}
- val = (uint16_t)(*((volatile uint16_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)));
- PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%08x", offset, val);
+ val = (uint16_t)(*((volatile uint16_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)));
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x", (unsigned long)offset, val);
return (val);
}
uint32_t val;
if ((offset % 4) != 0) {
- PMD_DRV_LOG(DEBUG, "Unaligned 32-bit read from 0x%08lx", offset);
+ PMD_DRV_LOG(NOTICE, "Unaligned 32-bit read from 0x%08lx",
+ (unsigned long)offset);
return 0;
}
- val = (uint32_t)(*((volatile uint32_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)));
- PMD_DRV_LOG(DEBUG, "offset=0x%08lx val=0x%08x", offset, val);
+ val = (uint32_t)(*((volatile uint32_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)));
+ PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x", (unsigned long)offset, val);
return (val);
}