Use new marker typedef available in EAL.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Acked-by: Matan Azrad <matan@mellanox.com>
/* separate cache line */
/* second cache line - fields only used in slow path */
- MARKER cacheline1 __rte_cache_min_aligned;
+ RTE_MARKER cacheline1 __rte_cache_min_aligned;
volatile uint32_t prod_index; /* step 2 filled by FPGA */
} __rte_cache_aligned;
uint32_t pad[1];
/* second cache line - fields only used in slow path */
- MARKER cacheline1 __rte_cache_min_aligned;
+ RTE_MARKER cacheline1 __rte_cache_min_aligned;
uint32_t cons_index; /* hw is done, can be freed */
} __rte_cache_aligned;
struct otx2_eth_dev {
OTX2_DEV; /* Base class */
- MARKER otx2_eth_dev_data_start;
+ RTE_MARKER otx2_eth_dev_data_start;
uint16_t sqb_size;
uint16_t rx_chan_base;
uint16_t tx_chan_base;
rte_iova_t fc_iova;
uint16_t sqes_per_sqb_log2;
int16_t nb_sqb_bufs_adj;
- MARKER slow_path_start;
+ RTE_MARKER slow_path_start;
uint16_t nb_sqb_bufs;
uint16_t sq;
uint64_t offloads;
uint32_t available;
uint16_t rq;
struct otx2_timesync_info *tstamp;
- MARKER slow_path_start;
+ RTE_MARKER slow_path_start;
uint64_t aura;
uint64_t offloads;
uint32_t qlen;
};
struct nicvf_rxq {
- MARKER rxq_fastpath_data_start;
+ RTE_MARKER rxq_fastpath_data_start;
uint8_t rbptr_offset;
uint16_t rx_free_thresh;
uint32_t head;
struct rte_mempool *pool;
union cq_entry_t *desc;
union mbuf_initializer mbuf_initializer;
- MARKER rxq_fastpath_data_end;
+ RTE_MARKER rxq_fastpath_data_end;
uint8_t rx_drop_en;
uint16_t precharge_cnt;
uint16_t port_id;