STATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw);
STATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
STATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
-static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
-static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
-static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
-static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
-static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
+STATIC s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
+STATIC s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
+STATIC s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
+STATIC s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
+STATIC s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
u16 *data);
-static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
+STATIC s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
u16 data);
-static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
-static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
+STATIC void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
+STATIC void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
STATIC s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
STATIC void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
* with a lower bound at "index" and the upper bound at
* "index + 5".
*/
-static const u16 e1000_gg82563_cable_length_table[] = {
+STATIC const u16 e1000_gg82563_cable_length_table[] = {
0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
#define GG82563_CABLE_LENGTH_TABLE_SIZE \
(sizeof(e1000_gg82563_cable_length_table) / \
* Acquire the SW/FW semaphore to access the PHY or NVM. The mask
* will also specify which port we're acquiring the lock for.
**/
-static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
+STATIC s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
{
u32 swfw_sync;
u32 swmask = mask;
* Release the SW/FW semaphore used to access the PHY or NVM. The mask
* will also specify which port we're releasing the lock for.
**/
-static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
+STATIC void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
{
u32 swfw_sync;
*
* Initializes required hardware-dependent bits needed for normal operation.
**/
-static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
+STATIC void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
{
u32 reg;
*
* Setup some GG82563 PHY registers for obtaining link
**/
-static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
+STATIC s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
{
struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
* Configure the KMRN interface by applying last minute quirks for
* 10/100 operation.
**/
-static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
+STATIC s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
{
s32 ret_val = E1000_SUCCESS;
u16 speed;
* Configure the KMRN interface by applying last minute quirks for
* 10/100 operation.
**/
-static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
+STATIC s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
{
s32 ret_val;
u32 tipg;
* Configure the KMRN interface by applying last minute quirks for
* gigabit operation.
**/
-static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
+STATIC s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
{
s32 ret_val;
u16 reg_data, reg_data2;
* using the kumeran interface. The information retrieved is stored in data.
* Release the semaphore before exiting.
**/
-static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
+STATIC s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
u16 *data)
{
u32 kmrnctrlsta;
* at the offset using the kumeran interface. Release semaphore
* before exiting.
**/
-static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
+STATIC s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
u16 data)
{
u32 kmrnctrlsta;
STATIC s32 e1000_init_phy_params_82540(struct e1000_hw *hw);
STATIC s32 e1000_init_nvm_params_82540(struct e1000_hw *hw);
STATIC s32 e1000_init_mac_params_82540(struct e1000_hw *hw);
-static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw);
+STATIC s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw);
STATIC void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw);
STATIC s32 e1000_init_hw_82540(struct e1000_hw *hw);
STATIC s32 e1000_reset_hw_82540(struct e1000_hw *hw);
-static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw);
-static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw);
+STATIC s32 e1000_set_phy_mode_82540(struct e1000_hw *hw);
+STATIC s32 e1000_set_vco_speed_82540(struct e1000_hw *hw);
STATIC s32 e1000_setup_copper_link_82540(struct e1000_hw *hw);
STATIC s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw);
STATIC void e1000_power_down_phy_copper_82540(struct e1000_hw *hw);
*
* Adjust the SERDES output amplitude based on the EEPROM settings.
**/
-static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
+STATIC s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
{
s32 ret_val = E1000_SUCCESS;
u16 nvm_data;
*
* Set the VCO speed to improve Bit Error Rate (BER) performance.
**/
-static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
+STATIC s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
{
s32 ret_val = E1000_SUCCESS;
u16 default_page = 0;
* 1. Do a PHY soft reset.
* 2. Restart auto-negotiation or force link.
**/
-static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)
+STATIC s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)
{
s32 ret_val = E1000_SUCCESS;
u16 nvm_data;
STATIC s32 e1000_setup_led_82541(struct e1000_hw *hw);
STATIC s32 e1000_cleanup_led_82541(struct e1000_hw *hw);
STATIC void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw);
-static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
+STATIC s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
bool link_up);
-static s32 e1000_phy_init_script_82541(struct e1000_hw *hw);
+STATIC s32 e1000_phy_init_script_82541(struct e1000_hw *hw);
STATIC void e1000_power_down_phy_copper_82541(struct e1000_hw *hw);
-static const u16 e1000_igp_cable_length_table[] = {
+STATIC const u16 e1000_igp_cable_length_table[] = {
5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 10, 10, 10, 10, 10,
10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 25, 25, 25, 25, 30, 30, 30, 30,
40, 40, 40, 40, 40, 40, 40, 40, 40, 50, 50, 50, 50, 50, 50, 50, 60, 60,
* 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
* gigabit link is achieved to improve link quality.
**/
-static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
+STATIC s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
bool link_up)
{
struct e1000_phy_info *phy = &hw->phy;
*
* Initializes the IGP PHY.
**/
-static s32 e1000_phy_init_script_82541(struct e1000_hw *hw)
+STATIC s32 e1000_phy_init_script_82541(struct e1000_hw *hw)
{
struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
u32 ret_val;
STATIC void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset,
u32 value);
STATIC void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw);
-static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw);
-static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw);
-static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
-static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw);
-static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
-static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw);
-static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
+STATIC s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw);
+STATIC bool e1000_init_phy_disabled_82543(struct e1000_hw *hw);
+STATIC void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
+STATIC s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw);
+STATIC void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
+STATIC u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw);
+STATIC void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
u16 count);
-static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw);
-static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state);
+STATIC bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw);
+STATIC void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state);
/**
* e1000_init_phy_params_82543 - Init PHY func ptrs.
* Returns the current status of 10-bit Interface (TBI) compatibility
* (enabled/disabled).
**/
-static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw)
+STATIC bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw)
{
struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
bool state = false;
*
* Enables or disabled 10-bit Interface (TBI) store bad packet (SBP).
**/
-static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state)
+STATIC void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state)
{
struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
* Returns the current status of whether PHY initialization is disabled.
* True if PHY initialization is disabled else false.
**/
-static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw)
+STATIC bool e1000_init_phy_disabled_82543(struct e1000_hw *hw)
{
struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
bool ret_val;
* Raise the management data input clock by setting the MDC bit in the control
* register.
**/
-static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
+STATIC void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
{
/*
* Raise the clock input to the Management Data Clock (by setting the
* Lower the management data input clock by clearing the MDC bit in the
* control register.
**/
-static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
+STATIC void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
{
/*
* Lower the clock input to the Management Data Clock (by clearing the
* "data" parameter will be shifted out to the PHY one bit at a time.
* In order to do this, "data" must be broken down into bits.
**/
-static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
+STATIC void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
u16 count)
{
u32 ctrl, mask;
* the PHY (setting the MDC bit), and then reading the value of the data out
* MDIO bit.
**/
-static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw)
+STATIC u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw)
{
u32 ctrl;
u16 data = 0;
* inadvertently. To workaround the issue, we disable the transmitter on
* the PHY until we have established the link partner's link parameters.
**/
-static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw)
+STATIC s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw)
{
s32 ret_val = E1000_SUCCESS;
u16 mii_status_reg;
* For the 82543 silicon, we need to set the MAC to match the settings
* of the PHY, even if the PHY is auto-negotiating.
**/
-static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw)
+STATIC s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw)
{
u32 ctrl;
s32 ret_val = E1000_SUCCESS;
STATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
STATIC s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
STATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
-static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
-static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
-static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
-static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
-static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
-static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
-static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
+STATIC s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
+STATIC s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
+STATIC s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
+STATIC void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
+STATIC void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
+STATIC s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
+STATIC void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
STATIC s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
bool active);
STATIC s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
bool active);
-static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
-static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
+STATIC void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
+STATIC s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
u16 words, u16 *data);
STATIC s32 e1000_read_mac_addr_82571(struct e1000_hw *hw);
STATIC void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
* Reads the PHY registers and stores the PHY ID and possibly the PHY
* revision in the hardware structure.
**/
-static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
+STATIC s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
{
struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
*
* Acquire the HW semaphore to access the PHY or NVM
**/
-static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
+STATIC s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
{
u32 swsm;
s32 sw_timeout = hw->nvm.word_size + 1;
*
* Release hardware semaphore used to access the PHY or NVM
**/
-static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
+STATIC void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
{
u32 swsm;
* Acquire the HW semaphore during reset.
*
**/
-static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
+STATIC s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
{
u32 extcnf_ctrl;
s32 i = 0;
* Release hardware semaphore used during reset.
*
**/
-static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
+STATIC void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
{
u32 extcnf_ctrl;
* Acquire the HW semaphore to access the PHY or NVM.
*
**/
-static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
+STATIC s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
{
s32 ret_val;
* Release hardware semaphore used to access the PHY or NVM
*
**/
-static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
+STATIC void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
{
DEBUGFUNC("e1000_put_hw_semaphore_82574");
* If e1000_update_nvm_checksum is not called after this function, the
* EEPROM will most likely contain an invalid checksum.
**/
-static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
+STATIC s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
u16 words, u16 *data)
{
struct e1000_nvm_info *nvm = &hw->nvm;
*
* Initializes required hardware-dependent bits needed for normal operation.
**/
-static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
+STATIC void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
{
u32 reg;
* the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
* we need to return bad checksum.
**/
-static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
+STATIC s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
{
struct e1000_nvm_info *nvm = &hw->nvm;
s32 ret_val;
u32 offset, u16 data);
STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
-static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
+STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
u16 *speed, u16 *duplex);
-static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
+STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
-static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
+STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw);
STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);
STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
STATIC bool e1000_get_i2c_data(u32 *i2cctl);
-static const u16 e1000_82580_rxpbs_table[] = {
+STATIC const u16 e1000_82580_rxpbs_table[] = {
36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
#define E1000_82580_RXPBS_TABLE_SIZE \
- (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
+ (sizeof(e1000_82580_rxpbs_table) / \
+ sizeof(e1000_82580_rxpbs_table[0]))
/**
* Using the physical coding sub-layer (PCS), retrieve the current speed and
* duplex, then store the values in the pointers provided.
**/
-static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
+STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
u16 *speed, u16 *duplex)
{
struct e1000_mac_info *mac = &hw->mac;
* which can be enabled for use in the embedded applications. Simply
* return the current state of the sgmii interface.
**/
-static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
+STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw)
{
struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
return dev_spec->sgmii_active;
#include "e1000_api.h"
-static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
+STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw);
STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
-static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
-static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
+STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
+STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
u32 offset, u8 *data);
-static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
+STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
u8 size, u16 *data);
STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
u32 offset, u16 *data);
-static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
+STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
u32 offset, u8 byte);
STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
-static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
+STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
*
* Assumes the sw/fw/hw semaphore is already acquired.
**/
-static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
+STATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
{
u16 phy_reg = 0;
u32 phy_id = 0;
* Toggling the LANPHYPC pin value fully power-cycles the PHY and is
* used to reset the PHY to a quiescent state when necessary.
**/
-void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
+STATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
{
u32 mac_reg;
* Workarounds/flow necessary for PHY initialization during driver load
* and resume paths.
**/
-static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
+STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
{
u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
s32 ret_val;
* Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
* speeds in order to avoid Tx hangs.
**/
-static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
+STATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
{
u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
u32 status = E1000_READ_REG(hw, E1000_STATUS);
* change in link status has been detected, then we read the PHY registers
* to get the current speed/duplex if link exists.
**/
-static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
+STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
{
struct e1000_mac_info *mac = &hw->mac;
s32 ret_val;
fwsm = E1000_READ_REG(hw, E1000_FWSM);
- return ((fwsm & E1000_ICH_FWSM_FW_VALID) &&
- ((fwsm & E1000_FWSM_MODE_MASK) ==
- (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)));
+ return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
+ ((fwsm & E1000_FWSM_MODE_MASK) ==
+ (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
}
/**
* collectively called OEM bits. The OEM Write Enable bit and SW Config bit
* in NVM determines whether HW should configure LPLU and Gbe Disable.
**/
-static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
+STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
{
s32 ret_val = 0;
u32 mac_reg;
}
#ifndef CRC32_OS_SUPPORT
-static u32 e1000_calc_rx_da_crc(u8 mac[])
+STATIC u32 e1000_calc_rx_da_crc(u8 mac[])
{
u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
u32 i, j, mask, crc;
* This function does initial flash setup so that a new read/write/erase cycle
* can be started.
**/
-static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
+STATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
{
union ich8_hws_flash_status hsfsts;
s32 ret_val = -E1000_ERR_NVM;
/* Clear FCERR and DAEL in hw status by writing 1 */
hsfsts.hsf_status.flcerr = 1;
hsfsts.hsf_status.dael = 1;
-
E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
/* Either we should have a hardware SPI cycle in progress
*
* This function starts a flash cycle and waits for its completion.
**/
-static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
+STATIC s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
{
union ich8_hws_flash_ctrl hsflctl;
union ich8_hws_flash_status hsfsts;
/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
hsflctl.hsf_ctrl.flcgo = 1;
+
E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
/* wait till FDONE bit is set to 1 */
u16 word = 0;
ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
+
if (ret_val)
return ret_val;
*
* Reads a byte or word from the NVM using the flash access registers.
**/
-static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
+STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
u8 size, u16 *data)
{
union ich8_hws_flash_status hsfsts;
if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
return -E1000_ERR_NVM;
-
flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
hw->nvm.flash_base_addr);
ret_val = e1000_flash_cycle_init_ich8lan(hw);
if (ret_val != E1000_SUCCESS)
break;
-
hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
+
/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
hsflctl.hsf_ctrl.fldbcount = size - 1;
hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
*
* Writes one/two bytes to the NVM using the flash access registers.
**/
-static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
+STATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
u8 size, u16 data)
{
union ich8_hws_flash_status hsfsts;
ret_val = e1000_flash_cycle_init_ich8lan(hw);
if (ret_val != E1000_SUCCESS)
break;
-
hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
+
/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
hsflctl.hsf_ctrl.fldbcount = size - 1;
hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
* Writes a single byte to the NVM using the flash access registers.
* Goes through a retry algorithm before giving up.
**/
-static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
+STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
u32 offset, u8 byte)
{
s32 ret_val;
/* Write a value 11 (block Erase) in Flash
* Cycle field in hw flash control
*/
- hsflctl.regval = E1000_READ_FLASH_REG16(hw,
- ICH_FLASH_HSFCTL);
+ hsflctl.regval =
+ E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
+
hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
hsflctl.regval);
* Sets/Clears required hardware bits necessary for correctly setting up the
* hardware for transmit and receive.
**/
-static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
+STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
{
u32 reg;
* 5) repeat up to 10 times
* Note: this is only called for IGP3 copper when speed is 1gb.
**/
-static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
+STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
{
struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
u32 phy_ctrl;
* The SMBus release must also be disabled on LCD reset.
*/
if (!(E1000_READ_REG(hw, E1000_FWSM) &
- E1000_ICH_FWSM_FW_VALID)) {
+ E1000_ICH_FWSM_FW_VALID)) {
/* Enable proxy to reset only on power good. */
hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
&phy_reg);
#if defined(NAHUM6LP_HW) && defined(ULP_SUPPORT)
s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx);
s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
-void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw);
#endif /* NAHUM6LP_HW && ULP_SUPPORT */
#endif /* _E1000_ICH8LAN_H_ */
void e1000_demote_ltr(struct e1000_hw *hw, bool demote, bool link);
*
* Enable/Raise the EEPROM clock bit.
**/
-static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
+STATIC void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
{
*eecd = *eecd | E1000_EECD_SK;
E1000_WRITE_REG(hw, E1000_EECD, *eecd);
*
* Clear/Lower the EEPROM clock bit.
**/
-static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
+STATIC void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
{
*eecd = *eecd & ~E1000_EECD_SK;
E1000_WRITE_REG(hw, E1000_EECD, *eecd);
* "data" parameter will be shifted out to the EEPROM one bit at a time.
* In order to do this, "data" must be broken down into bits.
**/
-static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
+STATIC void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
{
struct e1000_nvm_info *nvm = &hw->nvm;
u32 eecd = E1000_READ_REG(hw, E1000_EECD);
* "DO" bit. During this "shifting in" process the data in "DI" bit should
* always be clear.
**/
-static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
+STATIC u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
{
u32 eecd;
u32 i;
*
* Return the EEPROM to a standby state.
**/
-static void e1000_standby_nvm(struct e1000_hw *hw)
+STATIC void e1000_standby_nvm(struct e1000_hw *hw)
{
struct e1000_nvm_info *nvm = &hw->nvm;
u32 eecd = E1000_READ_REG(hw, E1000_EECD);
*
* Setups the EEPROM for reading and writing.
**/
-static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
+STATIC s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
{
struct e1000_nvm_info *nvm = &hw->nvm;
u32 eecd = E1000_READ_REG(hw, E1000_EECD);
#include "e1000_api.h"
-static s32 e1000_wait_autoneg(struct e1000_hw *hw);
+STATIC s32 e1000_wait_autoneg(struct e1000_hw *hw);
STATIC s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
u16 *data, bool read, bool page_set);
STATIC u32 e1000_get_phy_addr_for_hv_page(u32 page);
u16 *data, bool read);
/* Cable length tables */
-static const u16 e1000_m88_cable_length_table[] = {
+STATIC const u16 e1000_m88_cable_length_table[] = {
0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
(sizeof(e1000_m88_cable_length_table) / \
sizeof(e1000_m88_cable_length_table[0]))
-static const u16 e1000_igp_2_cable_length_table[] = {
+STATIC const u16 e1000_igp_2_cable_length_table[] = {
0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
* and stores the retrieved information in data. Release any acquired
* semaphores before exiting.
**/
-static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
+STATIC s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
bool locked)
{
s32 ret_val = E1000_SUCCESS;
* Acquires semaphore, if necessary, then writes the data to PHY register
* at the offset. Release any acquired semaphores before exiting.
**/
-static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
+STATIC s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
bool locked)
{
s32 ret_val = E1000_SUCCESS;
* using the kumeran interface. The information retrieved is stored in data.
* Release any acquired semaphores before exiting.
**/
-static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
+STATIC s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
bool locked)
{
u32 kmrnctrlsta;
* at the offset using the kumeran interface. Release any acquired semaphores
* before exiting.
**/
-static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
+STATIC s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
bool locked)
{
u32 kmrnctrlsta;
* Waits for auto-negotiation to complete or for the auto-negotiation time
* limit to expire, which ever happens first.
**/
-static s32 e1000_wait_autoneg(struct e1000_hw *hw)
+STATIC s32 e1000_wait_autoneg(struct e1000_hw *hw)
{
s32 ret_val = E1000_SUCCESS;
u16 i, phy_status;
*
* Returns the phy address for the page requested.
**/
-static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
+STATIC u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
{
u32 phy_addr = 2;
* and stores the retrieved information in data. Release any acquired
* semaphore before exiting.
**/
-static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
+STATIC s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
bool locked, bool page_set)
{
s32 ret_val;
* Acquires semaphore, if necessary, then writes the data to PHY register
* at the offset. Release any acquired semaphores before exiting.
**/
-static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
+STATIC s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
bool locked, bool page_set)
{
s32 ret_val;
{
u32 mphy_ctrl = 0;
bool locked = false;
- bool ready = false;
+ bool ready;
DEBUGFUNC("e1000_read_phy_reg_mphy");
{
u32 mphy_ctrl = 0;
bool locked = false;
- bool ready = false;
+ bool ready;
DEBUGFUNC("e1000_write_phy_reg_mphy");
return hash_value;
}
-static void e1000_write_msg_read_ack(struct e1000_hw *hw,
+STATIC void e1000_write_msg_read_ack(struct e1000_hw *hw,
u32 *msg, u16 size)
{
struct e1000_mbx_info *mbx = &hw->mbx;
git.droids-corp.org / dpdk.git / commitdiff