net/qede/base: refactor some code bits

Bits of code refactoring in ecore_hw_bar_size(), ecore_get_hw_info()
and ecore_init_cmd_*.

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>

diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c
index f7a36c9..b754028 100644 (file)
--- a/drivers/net/qede/base/ecore_dev.c
+++ b/drivers/net/qede/base/ecore_dev.c
@@ -70,28 +70,26 @@ static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
        }
 
        val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
+       if (val)
+               return 1 << (val + 15);
 
        /* The above registers were updated in the past only in CMT mode. Since
         * they were found to be useful MFW started updating them from 8.7.7.0.
         * In older MFW versions they are set to 0 which means disabled.
         */
-       if (!val) {
-               if (p_hwfn->p_dev->num_hwfns > 1) {
-                       DP_NOTICE(p_hwfn, false,
-                                 "BAR size not configured. Assuming BAR size");
-                       DP_NOTICE(p_hwfn, false,
-                                 "of 256kB for GRC and 512kB for DB\n");
-                       return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
-               } else {
-                       DP_NOTICE(p_hwfn, false,
-                                 "BAR size not configured. Assuming BAR size");
-                       DP_NOTICE(p_hwfn, false,
-                                 "of 512kB for GRC and 512kB for DB\n");
-                       return 512 * 1024;
-               }
+       if (p_hwfn->p_dev->num_hwfns > 1) {
+               DP_NOTICE(p_hwfn, false,
+                         "BAR size not configured. Assuming BAR size of 256kB"
+                         " for GRC and 512kB for DB\n");
+               val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
+       } else {
+               DP_NOTICE(p_hwfn, false,
+                         "BAR size not configured. Assuming BAR size of 512kB"
+                         " for GRC and 512kB for DB\n");
+               val = 512 * 1024;
        }
 
-       return 1 << (val + 15);
+       return val;
 }
 
 void ecore_init_dp(struct ecore_dev *p_dev,
@@ -2785,11 +2783,14 @@ ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
                ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
        }
 
-       if (personality != ECORE_PCI_DEFAULT)
+       if (personality != ECORE_PCI_DEFAULT) {
                p_hwfn->hw_info.personality = personality;
-       else if (ecore_mcp_is_init(p_hwfn))
-               p_hwfn->hw_info.personality =
-                   p_hwfn->mcp_info->func_info.protocol;
+       } else if (ecore_mcp_is_init(p_hwfn)) {
+               enum ecore_pci_personality protocol;
+
+               protocol = p_hwfn->mcp_info->func_info.protocol;
+               p_hwfn->hw_info.personality = protocol;
+       }
 
 #ifndef ASIC_ONLY
        /* To overcome ILT lack for emulation, until at least until we'll have

diff --git a/drivers/net/qede/base/ecore_init_ops.c b/drivers/net/qede/base/ecore_init_ops.c
index a6ed590..b907a95 100644 (file)
--- a/drivers/net/qede/base/ecore_init_ops.c
+++ b/drivers/net/qede/base/ecore_init_ops.c
@@ -190,19 +190,19 @@ static enum _ecore_status_t ecore_init_cmd_array(struct ecore_hwfn *p_hwfn,
                                                 bool b_must_dmae,
                                                 bool b_can_dmae)
 {
+       u32 dmae_array_offset = OSAL_LE32_TO_CPU(cmd->args.array_offset);
+       u32 data = OSAL_LE32_TO_CPU(cmd->data);
+       u32 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2;
 #ifdef CONFIG_ECORE_ZIPPED_FW
        u32 offset, output_len, input_len, max_size;
 #endif
-       u32 dmae_array_offset = OSAL_LE32_TO_CPU(cmd->args.array_offset);
        struct ecore_dev *p_dev = p_hwfn->p_dev;
-       enum _ecore_status_t rc = ECORE_SUCCESS;
        union init_array_hdr *hdr;
        const u32 *array_data;
-       u32 size, addr, data;
+       enum _ecore_status_t rc = ECORE_SUCCESS;
+       u32 size;
 
        array_data = p_dev->fw_data->arr_data;
-       data = OSAL_LE32_TO_CPU(cmd->data);
-       addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2;
 
        hdr = (union init_array_hdr *)
                (uintptr_t)(array_data + dmae_array_offset);
@@ -272,13 +272,10 @@ static enum _ecore_status_t ecore_init_cmd_wr(struct ecore_hwfn *p_hwfn,
                                              struct init_write_op *p_cmd,
                                              bool b_can_dmae)
 {
+       u32 data = OSAL_LE32_TO_CPU(p_cmd->data);
+       bool b_must_dmae = GET_FIELD(data, INIT_WRITE_OP_WIDE_BUS);
+       u32 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2;
        enum _ecore_status_t rc = ECORE_SUCCESS;
-       bool b_must_dmae;
-       u32 addr, data;
-
-       data = OSAL_LE32_TO_CPU(p_cmd->data);
-       b_must_dmae = GET_FIELD(data, INIT_WRITE_OP_WIDE_BUS);
-       addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2;
 
        /* Sanitize */
        if (b_must_dmae && !b_can_dmae) {