relaxed_ordering_write);
        attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
                        relaxed_ordering_read);
+       attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
+                       access_register_user);
        attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
                                          eth_net_offloads);
        attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
 
        uint32_t vhca_id:16;
        uint32_t relaxed_ordering_write:1;
        uint32_t relaxed_ordering_read:1;
+       uint32_t access_register_user:1;
        uint32_t wqe_index_ignore:1;
        uint32_t cross_channel:1;
        uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */
 
        u8 log_max_eq_sz[0x8];
        u8 relaxed_ordering_write[0x1];
        u8 relaxed_ordering_read[0x1];
-       u8 log_max_mkey[0x6];
+       u8 access_register_user[0x1];
+       u8 log_max_mkey[0x5];
        u8 reserved_at_f0[0x8];
        u8 dump_fill_mkey[0x1];
        u8 reserved_at_f9[0x3];
 
        if (config->devx) {
                uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];
 
-               err = mlx5_devx_cmd_register_read
-                       (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0,
-                       reg, MLX5_ST_SZ_DW(register_mtutc));
+               err = config->hca_attr.access_register_user ?
+                       mlx5_devx_cmd_register_read
+                               (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0,
+                               reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP;
                if (!err) {
                        uint32_t ts_mode;