baseband/fpga_5gnr_fec: remove FLR timeout

FLR timeout register is not used in 5GNR FPGA.

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Nicolas Chautru <nicolas.chautru@intel.com>

diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index 0fa119a5028b921dd8684cb80dec67f616531a8d..fad3b1e49d0a872091604d52fb63c0cf1a9376a1 100644 (file)
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -50,7 +50,6 @@
 #define DL_5G_BANDWIDTH 3
 #define UL_5G_LOAD_BALANCE 128
 #define DL_5G_LOAD_BALANCE 128
-#define FLR_5G_TIMEOUT 610
 #endif
 
 #ifdef RTE_BASEBAND_ACC100
@@ -699,9 +698,6 @@ add_bbdev_dev(uint8_t dev_id, struct rte_bbdev_info *info,
                conf.ul_load_balance = UL_5G_LOAD_BALANCE;
                conf.dl_load_balance = DL_5G_LOAD_BALANCE;
 
-               /**< FLR timeout value */
-               conf.flr_time_out = FLR_5G_TIMEOUT;
-
                /* setup FPGA PF with configuration information */
                ret = rte_fpga_5gnr_fec_configure(info->dev_name, &conf);
                TEST_ASSERT_SUCCESS(ret,

diff --git a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h
index e72c95e93687552053f9388ccf048326bcf5499e..ed8ce26eaa774a6e7b43b6b2156245a118c23337 100644 (file)
--- a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h
+++ b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h
@@ -36,7 +36,6 @@
 #define FPGA_RING_DESC_LEN_UNIT_BYTES (32)
 /* Maximum size of queue */
 #define FPGA_RING_MAX_SIZE (1024)
-#define FPGA_FLR_TIMEOUT_UNIT (16.384)
 
 #define FPGA_NUM_UL_QUEUES (32)
 #define FPGA_NUM_DL_QUEUES (32)
@@ -70,7 +69,6 @@ enum {
        FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE = 0x00000008, /* len: 1B */
        FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR = 0x0000000a, /* len: 2B */
        FPGA_5GNR_FEC_RING_DESC_LEN = 0x0000000c, /* len: 2B */
-       FPGA_5GNR_FEC_FLR_TIME_OUT = 0x0000000e, /* len: 2B */
        FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW = 0x00000018, /* len: 4B */
        FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI = 0x0000001c, /* len: 4B */
        FPGA_5GNR_FEC_QUEUE_MAP = 0x00000040, /* len: 256B */

diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c
index 15d23d626913624b4032189f3c08fd0548964385..6737b7490102182c359af9377adb5e7211cb81ad 100644 (file)
--- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c
+++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c
@@ -83,8 +83,6 @@ print_static_reg_debug_info(void *mmio_base)
                        FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR);
        uint16_t ring_desc_len = fpga_reg_read_16(mmio_base,
                        FPGA_5GNR_FEC_RING_DESC_LEN);
-       uint16_t flr_time_out = fpga_reg_read_16(mmio_base,
-                       FPGA_5GNR_FEC_FLR_TIME_OUT);
 
        rte_bbdev_log_debug("UL.DL Weights = %u.%u",
                        ((uint8_t)config), ((uint8_t)(config >> 8)));
@@ -94,8 +92,6 @@ print_static_reg_debug_info(void *mmio_base)
                        (qmap_done > 0) ? "READY" : "NOT-READY");
        rte_bbdev_log_debug("Ring Descriptor Size = %u bytes",
                        ring_desc_len*FPGA_RING_DESC_LEN_UNIT_BYTES);
-       rte_bbdev_log_debug("FLR Timeout = %f usec",
-                       (float)flr_time_out*FPGA_FLR_TIMEOUT_UNIT);
 }
 
 /* Print decode DMA Descriptor of FPGA 5GNR Decoder device */
@@ -2120,11 +2116,6 @@ rte_fpga_5gnr_fec_configure(const char *dev_name,
        address = FPGA_5GNR_FEC_RING_DESC_LEN;
        fpga_reg_write_16(d->mmio_base, address, payload_16);
 
-       /* Setting FLR timeout value */
-       payload_16 = conf->flr_time_out;
-       address = FPGA_5GNR_FEC_FLR_TIME_OUT;
-       fpga_reg_write_16(d->mmio_base, address, payload_16);
-
        /* Queue PF/VF mapping table is ready */
        payload_8 = 0x1;
        address = FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE;

diff --git a/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h
index c2752fbd52d72b25bf37b96db2455955bedc885b..93a87c8e82238ac8721c7c16d733059f6b20777c 100644 (file)
--- a/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h
+++ b/drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h
@@ -45,8 +45,6 @@ struct rte_fpga_5gnr_fec_conf {
        uint8_t ul_load_balance;
        /** DL Load Balance */
        uint8_t dl_load_balance;
-       /** FLR timeout value */
-       uint16_t flr_time_out;
 };
 
 /**