u8 pi = bm_in(RCR_PI_CINH) & (BM_RCR_SIZE - 1);
u8 ci = bm_in(RCR_CI_CINH) & (BM_RCR_SIZE - 1);
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(!rcr->busy);
+#endif
if (pi != RCR_PTR2IDX(rcr->cursor))
pr_crit("losing uncommitted RCR entries\n");
if (ci != rcr->ci)
{
register struct bm_rcr *rcr = &portal->rcr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(!rcr->busy);
+#endif
if (!rcr->available)
return NULL;
#ifdef RTE_LIBRTE_DPAA_HWDEBUG
{
__maybe_unused register struct bm_rcr *rcr = &portal->rcr;
- DPAA_ASSERT(rcr->busy);
#ifdef RTE_LIBRTE_DPAA_HWDEBUG
+ DPAA_ASSERT(rcr->busy);
rcr->busy = 0;
#endif
}
{
register struct bm_rcr *rcr = &portal->rcr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(rcr->busy);
DPAA_ASSERT(rcr->pmode != bm_rcr_pvb);
+#endif
if (rcr->available == 1)
return NULL;
rcr->cursor->__dont_write_directly__verb = myverb | rcr->vbit;
{
register struct bm_rcr *rcr = &portal->rcr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(rcr->busy);
DPAA_ASSERT(rcr->pmode == bm_rcr_pci);
+#endif
rcr->cursor->__dont_write_directly__verb = myverb | rcr->vbit;
RCR_INC(rcr);
rcr->available--;
{
__maybe_unused register struct bm_rcr *rcr = &portal->rcr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(rcr->pmode == bm_rcr_pce);
+#endif
bm_cl_invalidate(RCR_PI);
bm_cl_touch_rw(RCR_PI);
}
{
register struct bm_rcr *rcr = &portal->rcr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(rcr->busy);
DPAA_ASSERT(rcr->pmode == bm_rcr_pce);
+#endif
rcr->cursor->__dont_write_directly__verb = myverb | rcr->vbit;
RCR_INC(rcr);
rcr->available--;
register struct bm_rcr *rcr = &portal->rcr;
struct bm_rcr_entry *rcursor;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(rcr->busy);
DPAA_ASSERT(rcr->pmode == bm_rcr_pvb);
+#endif
lwsync();
rcursor = rcr->cursor;
rcursor->__dont_write_directly__verb = myverb | rcr->vbit;
register struct bm_rcr *rcr = &portal->rcr;
u8 diff, old_ci = rcr->ci;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(rcr->cmode == bm_rcr_cci);
+#endif
rcr->ci = bm_in(RCR_CI_CINH) & (BM_RCR_SIZE - 1);
diff = bm_cyc_diff(BM_RCR_SIZE, old_ci, rcr->ci);
rcr->available += diff;
{
__maybe_unused register struct bm_rcr *rcr = &portal->rcr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(rcr->cmode == bm_rcr_cce);
+#endif
bm_cl_touch_ro(RCR_CI);
}
register struct bm_rcr *rcr = &portal->rcr;
u8 diff, old_ci = rcr->ci;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(rcr->cmode == bm_rcr_cce);
+#endif
rcr->ci = bm_cl_in(RCR_CI) & (BM_RCR_SIZE - 1);
bm_cl_invalidate(RCR_CI);
diff = bm_cyc_diff(BM_RCR_SIZE, old_ci, rcr->ci);
{
__maybe_unused register struct bm_mc *mc = &portal->mc;
- DPAA_ASSERT(mc->state == mc_idle);
#ifdef RTE_LIBRTE_DPAA_HWDEBUG
+ DPAA_ASSERT(mc->state == mc_idle);
if (mc->state != mc_idle)
pr_crit("Losing incomplete MC command\n");
#endif
{
register struct bm_mc *mc = &portal->mc;
- DPAA_ASSERT(mc->state == mc_idle);
#ifdef RTE_LIBRTE_DPAA_HWDEBUG
+ DPAA_ASSERT(mc->state == mc_idle);
mc->state = mc_user;
#endif
dcbz_64(mc->cr);
{
__maybe_unused register struct bm_mc *mc = &portal->mc;
- DPAA_ASSERT(mc->state == mc_user);
#ifdef RTE_LIBRTE_DPAA_HWDEBUG
+ DPAA_ASSERT(mc->state == mc_user);
mc->state = mc_idle;
#endif
}
register struct bm_mc *mc = &portal->mc;
struct bm_mc_result *rr = mc->rr + mc->rridx;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(mc->state == mc_user);
+#endif
lwsync();
mc->cr->__dont_write_directly__verb = myverb | mc->vbit;
dcbf(mc->cr);
register struct bm_mc *mc = &portal->mc;
struct bm_mc_result *rr = mc->rr + mc->rridx;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(mc->state == mc_hw);
+#endif
/* The inactive response register's verb byte always returns zero until
* its command is submitted and completed. This includes the valid-bit,
* in case you were wondering.
{
register struct qm_eqcr *eqcr = &portal->eqcr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(!eqcr->busy);
+#endif
if (!eqcr->available)
return NULL;
register struct qm_eqcr *eqcr = &portal->eqcr;
u8 diff, old_ci;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(!eqcr->busy);
+#endif
if (!eqcr->available) {
old_ci = eqcr->ci;
eqcr->ci = qm_cl_in(EQCR_CI) & (QM_EQCR_SIZE - 1);
{
__maybe_unused register struct qm_eqcr *eqcr = &portal->eqcr;
- DPAA_ASSERT(eqcr->busy);
#ifdef RTE_LIBRTE_DPAA_HWDEBUG
+ DPAA_ASSERT(eqcr->busy);
eqcr->busy = 0;
#endif
}
{
register struct qm_eqcr *eqcr = &portal->eqcr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(eqcr->busy);
DPAA_ASSERT(eqcr->pmode != qm_eqcr_pvb);
+#endif
if (eqcr->available == 1)
return NULL;
eqcr->cursor->__dont_write_directly__verb = myverb | eqcr->vbit;
{
register struct qm_eqcr *eqcr = &portal->eqcr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
EQCR_COMMIT_CHECKS(eqcr);
DPAA_ASSERT(eqcr->pmode == qm_eqcr_pci);
+#endif
eqcr->cursor->__dont_write_directly__verb = myverb | eqcr->vbit;
EQCR_INC(eqcr);
eqcr->available--;
{
__maybe_unused register struct qm_eqcr *eqcr = &portal->eqcr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(eqcr->pmode == qm_eqcr_pce);
+#endif
qm_cl_invalidate(EQCR_PI);
qm_cl_touch_rw(EQCR_PI);
}
{
register struct qm_eqcr *eqcr = &portal->eqcr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
EQCR_COMMIT_CHECKS(eqcr);
DPAA_ASSERT(eqcr->pmode == qm_eqcr_pce);
+#endif
eqcr->cursor->__dont_write_directly__verb = myverb | eqcr->vbit;
EQCR_INC(eqcr);
eqcr->available--;
register struct qm_eqcr *eqcr = &portal->eqcr;
struct qm_eqcr_entry *eqcursor;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
EQCR_COMMIT_CHECKS(eqcr);
DPAA_ASSERT(eqcr->pmode == qm_eqcr_pvb);
+#endif
lwsync();
eqcursor = eqcr->cursor;
eqcursor->__dont_write_directly__verb = myverb | eqcr->vbit;
register struct qm_dqrr *dqrr = &portal->dqrr;
u8 diff, old_pi = dqrr->pi;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(dqrr->pmode == qm_dqrr_pci);
+#endif
dqrr->pi = qm_in(DQRR_PI_CINH) & (QM_DQRR_SIZE - 1);
diff = qm_cyc_diff(QM_DQRR_SIZE, old_pi, dqrr->pi);
dqrr->fill += diff;
{
__maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(dqrr->pmode == qm_dqrr_pce);
+#endif
qm_cl_invalidate(DQRR_PI);
qm_cl_touch_ro(DQRR_PI);
}
register struct qm_dqrr *dqrr = &portal->dqrr;
u8 diff, old_pi = dqrr->pi;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(dqrr->pmode == qm_dqrr_pce);
+#endif
dqrr->pi = qm_cl_in(DQRR_PI) & (QM_DQRR_SIZE - 1);
diff = qm_cyc_diff(QM_DQRR_SIZE, old_pi, dqrr->pi);
dqrr->fill += diff;
register struct qm_dqrr *dqrr = &portal->dqrr;
const struct qm_dqrr_entry *res = qm_cl(dqrr->ring, dqrr->pi);
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(dqrr->pmode == qm_dqrr_pvb);
+#endif
/* when accessing 'verb', use __raw_readb() to ensure that compiler
* inlining doesn't try to optimise out "excess reads".
*/
{
register struct qm_dqrr *dqrr = &portal->dqrr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cci);
+#endif
dqrr->ci = (dqrr->ci + num) & (QM_DQRR_SIZE - 1);
qm_out(DQRR_CI_CINH, dqrr->ci);
}
{
register struct qm_dqrr *dqrr = &portal->dqrr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cci);
+#endif
dqrr->ci = DQRR_PTR2IDX(dqrr->cursor);
qm_out(DQRR_CI_CINH, dqrr->ci);
}
{
__maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cce);
+#endif
qm_cl_invalidate(DQRR_CI);
qm_cl_touch_rw(DQRR_CI);
}
{
register struct qm_dqrr *dqrr = &portal->dqrr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cce);
+#endif
dqrr->ci = (dqrr->ci + num) & (QM_DQRR_SIZE - 1);
qm_cl_out(DQRR_CI, dqrr->ci);
}
{
register struct qm_dqrr *dqrr = &portal->dqrr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cce);
+#endif
dqrr->ci = DQRR_PTR2IDX(dqrr->cursor);
qm_cl_out(DQRR_CI, dqrr->ci);
}
{
__maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
+#endif
DPAA_ASSERT(idx < QM_DQRR_SIZE);
qm_out(DQRR_DCAP, (0 << 8) | /* S */
((park ? 1 : 0) << 6) | /* PK */
__maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
u8 idx = DQRR_PTR2IDX(dq);
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
+#endif
DPAA_ASSERT(idx < QM_DQRR_SIZE);
qm_out(DQRR_DCAP, (0 << 8) | /* DQRR_DCAP::S */
((park ? 1 : 0) << 6) | /* DQRR_DCAP::PK */
{
__maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
+#endif
qm_out(DQRR_DCAP, (1 << 8) | /* DQRR_DCAP::S */
((u32)bitmask << 16)); /* DQRR_DCAP::DCAP_CI */
dqrr->ci = qm_in(DQRR_CI_CINH) & (QM_DQRR_SIZE - 1);
{
__maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
+#endif
return qm_in(DQRR_CI_CINH) & (QM_DQRR_SIZE - 1);
}
{
__maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
+#endif
qm_cl_invalidate(DQRR_CI);
qm_cl_touch_ro(DQRR_CI);
}
{
__maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
+#endif
return qm_cl_in(DQRR_CI) & (QM_DQRR_SIZE - 1);
}
{
register struct qm_dqrr *dqrr = &portal->dqrr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(dqrr->cmode != qm_dqrr_cdc);
+#endif
return dqrr->ci;
}
{
__maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(dqrr->cmode != qm_dqrr_cdc);
+#endif
qm_out(DQRR_DCAP, (0 << 8) | /* S */
(1 << 6) | /* PK */
(idx & (QM_DQRR_SIZE - 1))); /* DCAP_CI */
{
register struct qm_dqrr *dqrr = &portal->dqrr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(dqrr->cmode != qm_dqrr_cdc);
+#endif
qm_out(DQRR_DCAP, (0 << 8) | /* S */
(1 << 6) | /* PK */
DQRR_PTR2IDX(dqrr->cursor)); /* DCAP_CI */
{
register struct qm_mr *mr = &portal->mr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(mr->cmode == qm_mr_cci);
+#endif
mr->ci = (mr->ci + num) & (QM_MR_SIZE - 1);
qm_out(MR_CI_CINH, mr->ci);
}
{
register struct qm_mr *mr = &portal->mr;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(mr->cmode == qm_mr_cci);
+#endif
mr->ci = MR_PTR2IDX(mr->cursor);
qm_out(MR_CI_CINH, mr->ci);
}
{
__maybe_unused register struct qm_mc *mc = &portal->mc;
- DPAA_ASSERT(mc->state == qman_mc_idle);
#ifdef RTE_LIBRTE_DPAA_HWDEBUG
+ DPAA_ASSERT(mc->state == qman_mc_idle);
if (mc->state != qman_mc_idle)
pr_crit("Losing incomplete MC command\n");
#endif
{
register struct qm_mc *mc = &portal->mc;
- DPAA_ASSERT(mc->state == qman_mc_idle);
#ifdef RTE_LIBRTE_DPAA_HWDEBUG
+ DPAA_ASSERT(mc->state == qman_mc_idle);
mc->state = qman_mc_user;
#endif
dcbz_64(mc->cr);
register struct qm_mc *mc = &portal->mc;
struct qm_mc_result *rr = mc->rr + mc->rridx;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(mc->state == qman_mc_user);
+#endif
lwsync();
mc->cr->__dont_write_directly__verb = myverb | mc->vbit;
dcbf(mc->cr);
register struct qm_mc *mc = &portal->mc;
struct qm_mc_result *rr = mc->rr + mc->rridx;
+#ifdef RTE_LIBRTE_DPAA_HWDEBUG
DPAA_ASSERT(mc->state == qman_mc_hw);
+#endif
/* The inactive response register's verb byte always returns zero until
* its command is submitted and completed. This includes the valid-bit,
* in case you were wondering.