net/hns3: support 200G speed rate
authorWei Hu (Xavier) <xavier.huwei@huawei.com>
Tue, 14 Jul 2020 06:16:07 +0000 (14:16 +0800)
committerFerruh Yigit <ferruh.yigit@intel.com>
Fri, 17 Jul 2020 16:21:21 +0000 (18:21 +0200)
The 200G device has a new device id 0xA228, so adds this device id
to pci table for pci driver can probe it. Similar to the network port
with other speed, the hns3 PMD driver gets 200G speed information
from firmware, and passes them to DPDK framework.

Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
drivers/net/hns3/hns3_cmd.h
drivers/net/hns3/hns3_ethdev.c
drivers/net/hns3/hns3_ethdev.h
drivers/net/hns3/hns3_ethdev_vf.c

index b203e66..d70f42e 100644 (file)
@@ -622,6 +622,7 @@ struct hns3_config_mac_mode_cmd {
 #define HNS3_CFG_SPEED_40G             3
 #define HNS3_CFG_SPEED_50G             4
 #define HNS3_CFG_SPEED_100G            5
+#define HNS3_CFG_SPEED_200G            8
 
 #define HNS3_CFG_SPEED_S               0
 #define HNS3_CFG_SPEED_M               GENMASK(5, 0)
index f218fb8..4712cc2 100644 (file)
@@ -2560,6 +2560,7 @@ hns3_dev_link_update(struct rte_eth_dev *eth_dev,
        case ETH_SPEED_NUM_40G:
        case ETH_SPEED_NUM_50G:
        case ETH_SPEED_NUM_100G:
+       case ETH_SPEED_NUM_200G:
                new_link.link_speed = mac->link_speed;
                break;
        default:
@@ -2789,6 +2790,9 @@ hns3_parse_speed(int speed_cmd, uint32_t *speed)
        case HNS3_CFG_SPEED_100G:
                *speed = ETH_SPEED_NUM_100G;
                break;
+       case HNS3_CFG_SPEED_200G:
+               *speed = ETH_SPEED_NUM_200G;
+               break;
        default:
                return -EINVAL;
        }
@@ -2811,7 +2815,8 @@ hns3_get_capability(struct hns3_hw *hw)
 
        if (device_id == HNS3_DEV_ID_25GE_RDMA ||
            device_id == HNS3_DEV_ID_50GE_RDMA ||
-           device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
+           device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
+           device_id == HNS3_DEV_ID_200G_RDMA)
                hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
 
        /* Get PCI revision id */
@@ -3027,6 +3032,10 @@ hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
                hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
                               HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
                break;
+       case ETH_SPEED_NUM_200G:
+               hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
+                              HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
+               break;
        default:
                PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
                return -EINVAL;
@@ -5589,6 +5598,7 @@ static const struct rte_pci_id pci_id_hns3_map[] = {
        { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
        { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
        { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
+       { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
        { .vendor_id = 0, /* sentinel */ },
 };
 
index 31d34b0..0e665e5 100644 (file)
@@ -23,6 +23,7 @@
 #define HNS3_DEV_ID_25GE_RDMA                  0xA222
 #define HNS3_DEV_ID_50GE_RDMA                  0xA224
 #define HNS3_DEV_ID_100G_RDMA_MACSEC           0xA226
+#define HNS3_DEV_ID_200G_RDMA                  0xA228
 #define HNS3_DEV_ID_100G_VF                    0xA22E
 #define HNS3_DEV_ID_100G_RDMA_PFC_VF           0xA22F
 
index 54e5dac..b881bbe 100644 (file)
@@ -1893,6 +1893,7 @@ hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
        case ETH_SPEED_NUM_40G:
        case ETH_SPEED_NUM_50G:
        case ETH_SPEED_NUM_100G:
+       case ETH_SPEED_NUM_200G:
                new_link.link_speed = mac->link_speed;
                break;
        default: