]> git.droids-corp.org - dpdk.git/commitdiff
vdpa/mlx5: fix completion queue assertion
authorMatan Azrad <matan@nvidia.com>
Wed, 2 Sep 2020 08:34:59 +0000 (08:34 +0000)
committerFerruh Yigit <ferruh.yigit@intel.com>
Fri, 18 Sep 2020 16:55:12 +0000 (18:55 +0200)
The CQ configuration enables the collapse feature in HW what cause HW to
write all the completions in the first CQE.
When this feature is enabled the HW doesn't switch the owner bit when it
starts a new cycle of the CQ, not like working without the collapse
feature.

The current SW CQ polling wrongly added an assertion to validate the
owner bit switch what causes a panic in debug mode.

Remove the aforementioned assertion.

Fixes: c5f714e50b0e ("vdpa/mlx5: optimize completion queue poll")
Cc: stable@dpdk.org
Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Xueming Li <xuemingl@nvidia.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
drivers/vdpa/mlx5/mlx5_vdpa_event.c

index bda547ffe0c982802119b9c62629b098931299eb..d0307b321ffbe94de41747b59da1e5d8b16b52ef 100644 (file)
@@ -213,8 +213,6 @@ mlx5_vdpa_cq_poll(struct mlx5_vdpa_cq *cq)
        comp = (cur_wqe_counter + 1u - next_wqe_counter) & cq_mask;
        if (comp) {
                cq->cq_ci += comp;
-               MLX5_ASSERT(!!(cq->cq_ci & cq_size) ==
-                           MLX5_CQE_OWNER(last_word.op_own));
                MLX5_ASSERT(MLX5_CQE_OPCODE(last_word.op_own) !=
                            MLX5_CQE_INVALID);
                if (unlikely(!(MLX5_CQE_OPCODE(last_word.op_own) ==