net/cxgbe: update link speeds and port modules

Add 25G and 100G link speeds and update supported port modules.

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>

diff --git a/drivers/net/cxgbe/base/common.h b/drivers/net/cxgbe/base/common.h
index 2520c0e..73ec057 100644 (file)
--- a/drivers/net/cxgbe/base/common.h
+++ b/drivers/net/cxgbe/base/common.h
@@ -231,8 +231,8 @@ struct adapter_params {
 struct link_config {
        unsigned short supported;        /* link capabilities */
        unsigned short advertising;      /* advertised capabilities */
-       unsigned short requested_speed;  /* speed user has requested */
-       unsigned short speed;            /* actual link speed */
+       unsigned int   requested_speed;  /* speed user has requested */
+       unsigned int   speed;            /* actual link speed */
        unsigned char  requested_fc;     /* flow control user has requested */
        unsigned char  fc;               /* actual link flow control */
        unsigned char  autoneg;          /* autonegotiating? */

diff --git a/drivers/net/cxgbe/base/t4_hw.c b/drivers/net/cxgbe/base/t4_hw.c
index 4ab12ac..05bf1e8 100644 (file)
--- a/drivers/net/cxgbe/base/t4_hw.c
+++ b/drivers/net/cxgbe/base/t4_hw.c
@@ -2522,9 +2522,8 @@ int t4_get_tp_version(struct adapter *adapter, u32 *vers)
                             1, vers, 0);
 }
 
-#define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
-               FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
-               FW_PORT_CAP_SPEED_100G | FW_PORT_CAP_ANEG)
+#define ADVERT_MASK (V_FW_PORT_CAP_SPEED(M_FW_PORT_CAP_SPEED) | \
+                    FW_PORT_CAP_ANEG)
 
 /**
  * t4_link_l1cfg - apply link configuration to MAC/PHY
@@ -2669,6 +2668,12 @@ const char *t4_get_port_type_description(enum fw_port_type port_type)
                "QSA",
                "QSFP",
                "BP40_BA",
+               "KR4_100G",
+               "CR4_QSFP",
+               "CR_QSFP",
+               "CR2_QSFP",
+               "SFP28",
+               "KR_SFP28",
        };
 
        if (port_type < ARRAY_SIZE(port_type_description))
@@ -3745,7 +3750,7 @@ int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
 
        if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
                /* link/module state change message */
-               int speed = 0, fc = 0, i;
+               unsigned int speed = 0, fc = 0, i;
                int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
                struct port_info *pi = NULL;
                struct link_config *lc;
@@ -3763,8 +3768,12 @@ int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
                        speed = ETH_SPEED_NUM_1G;
                else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
                        speed = ETH_SPEED_NUM_10G;
+               else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
+                       speed = ETH_SPEED_NUM_25G;
                else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
                        speed = ETH_SPEED_NUM_40G;
+               else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
+                       speed = ETH_SPEED_NUM_100G;
 
                for_each_port(adap, i) {
                        pi = adap2pinfo(adap, i);

diff --git a/drivers/net/cxgbe/base/t4fw_interface.h b/drivers/net/cxgbe/base/t4fw_interface.h
index 74f19fe..43e8c0a 100644 (file)
--- a/drivers/net/cxgbe/base/t4fw_interface.h
+++ b/drivers/net/cxgbe/base/t4fw_interface.h
@@ -1,7 +1,7 @@
 /*-
  *   BSD LICENSE
  *
- *   Copyright(c) 2014-2015 Chelsio Communications.
+ *   Copyright(c) 2014-2017 Chelsio Communications.
  *   All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
@@ -1061,7 +1061,7 @@ struct fw_vi_stats_cmd {
 enum fw_port_cap {
        FW_PORT_CAP_SPEED_100M          = 0x0001,
        FW_PORT_CAP_SPEED_1G            = 0x0002,
-       FW_PORT_CAP_SPEED_2_5G          = 0x0004,
+       FW_PORT_CAP_SPEED_25G           = 0x0004,
        FW_PORT_CAP_SPEED_10G           = 0x0008,
        FW_PORT_CAP_SPEED_40G           = 0x0010,
        FW_PORT_CAP_SPEED_100G          = 0x0020,
@@ -1077,6 +1077,12 @@ enum fw_port_cap {
        FW_PORT_CAP_802_3_ASM_DIR       = 0x8000,
 };
 
+#define S_FW_PORT_CAP_SPEED     0
+#define M_FW_PORT_CAP_SPEED     0x3f
+#define V_FW_PORT_CAP_SPEED(x)  ((x) << S_FW_PORT_CAP_SPEED)
+#define G_FW_PORT_CAP_SPEED(x) \
+       (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
+
 enum fw_port_mdi {
        FW_PORT_CAP_MDI_AUTO,
 };
@@ -1279,6 +1285,14 @@ enum fw_port_type {
        FW_PORT_TYPE_QSFP       = 14, /* No, 4, Yes, No, No, No, 40G */
        FW_PORT_TYPE_BP40_BA    = 15,
        /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
+       FW_PORT_TYPE_KR4_100G   = 16,   /* No, 4, 100G*/
+       FW_PORT_TYPE_CR4_QSFP   = 17,   /* No, 4, 100G*/
+       FW_PORT_TYPE_CR4_CFP4   = 18,   /* No, 4, 100G*/
+       FW_PORT_TYPE_CR_QSFP    = 19,   /* No, 1, 25G*/
+       FW_PORT_TYPE_CR_CFP4    = 20,   /* No, 1, 25G*/
+       FW_PORT_TYPE_CR2_QSFP   = 21,   /* No, 2, 50G*/
+       FW_PORT_TYPE_CR2_CFP4   = 22,   /* No, 2, 50G*/
+       FW_PORT_TYPE_SFP28      = 23,   /* No, 1, 25G*/
 
        FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
 };

diff --git a/drivers/net/cxgbe/cxgbe_main.c b/drivers/net/cxgbe/cxgbe_main.c
index 21e731f..4691505 100644 (file)
--- a/drivers/net/cxgbe/cxgbe_main.c
+++ b/drivers/net/cxgbe/cxgbe_main.c
@@ -206,9 +206,12 @@ static inline bool is_x_1g_port(const struct link_config *lc)
 
 static inline bool is_x_10g_port(const struct link_config *lc)
 {
-       return ((lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
-               (lc->supported & FW_PORT_CAP_SPEED_40G) != 0 ||
-               (lc->supported & FW_PORT_CAP_SPEED_100G) != 0);
+       unsigned int speeds, high_speeds;
+
+       speeds = V_FW_PORT_CAP_SPEED(G_FW_PORT_CAP_SPEED(lc->supported));
+       high_speeds = speeds & ~(FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G);
+
+       return high_speeds != 0;
 }
 
 inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
@@ -374,13 +377,17 @@ static void print_port_info(struct adapter *adap)
                char *bufp = buf;
 
                if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
-                       bufp += sprintf(bufp, "100/");
+                       bufp += sprintf(bufp, "100M/");
                if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
-                       bufp += sprintf(bufp, "1000/");
+                       bufp += sprintf(bufp, "1G/");
                if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
                        bufp += sprintf(bufp, "10G/");
+               if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G)
+                       bufp += sprintf(bufp, "25G/");
                if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
                        bufp += sprintf(bufp, "40G/");
+               if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G)
+                       bufp += sprintf(bufp, "100G/");
                if (bufp != buf)
                        --bufp;
                sprintf(bufp, "BASE-%s",
@@ -829,10 +836,10 @@ void t4_os_portmod_changed(const struct adapter *adap, int port_id)
                dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
                         mod_str[pi->mod_type]);
        else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
-               dev_info(adap, "Port%d: unsupported optical port module inserted\n",
+               dev_info(adap, "Port%d: unsupported port module inserted\n",
                         pi->port_id);
        else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
-               dev_info(adap, "Port%d: unknown port module inserted, forcing TWINAX\n",
+               dev_info(adap, "Port%d: unknown port module inserted\n",
                         pi->port_id);
        else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
                dev_info(adap, "Port%d: transceiver module error\n",