net/failsafe: register as Rx interrupt mode

This patch adds registering the Rx queues of the failsafe PMD with EAL
Rx interrupts subsystem.
Each failsafe RX queue is assigned with a unique eventfd and an enable
interrupts flag.
The PMD creates an interrupt vector containing the above eventfds and
Registers it with  EAL. The PMD also implements the Rx interrupts enable
and disable interface routines.
This patch does not implement the generation of Rx interrupts, so an
application can now wait for failsafe Rx interrupts but it will not
receive one.

Signed-off-by: Moti Haimovsky <motih@mellanox.com>
Acked-by: Gaetan Rivet <gaetan.rivet@6wind.com>

diff --git a/drivers/net/failsafe/Makefile b/drivers/net/failsafe/Makefile
index a3b8173aa759d4bb56df033961829c7bf83dd8f5..98a052610680eb50af7a307dcd3a9299db00130b 100644 (file)
--- a/drivers/net/failsafe/Makefile
+++ b/drivers/net/failsafe/Makefile
@@ -46,6 +46,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_PMD_FAILSAFE) += failsafe_ops.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_FAILSAFE) += failsafe_rxtx.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_FAILSAFE) += failsafe_ether.c
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_FAILSAFE) += failsafe_flow.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_FAILSAFE) += failsafe_intr.c
 
 # No exported include files
 

diff --git a/drivers/net/failsafe/failsafe.c b/drivers/net/failsafe/failsafe.c
index cb274eb76ffde1d687ef11586bda9dd5cba7aa64..921e6569e3e1c5ec7c3de6912a9970e4af1eb886 100644 (file)
--- a/drivers/net/failsafe/failsafe.c
+++ b/drivers/net/failsafe/failsafe.c
@@ -244,6 +244,10 @@ fs_eth_dev_create(struct rte_vdev_device *vdev)
                mac->addr_bytes[2], mac->addr_bytes[3],
                mac->addr_bytes[4], mac->addr_bytes[5]);
        dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
+       PRIV(dev)->intr_handle = (struct rte_intr_handle){
+               .fd = -1,
+               .type = RTE_INTR_HANDLE_EXT,
+       };
        return 0;
 free_args:
        failsafe_args_free(dev);

diff --git a/drivers/net/failsafe/failsafe_intr.c b/drivers/net/failsafe/failsafe_intr.c
new file mode 100644 (file)
index 0000000..8829ca4
--- /dev/null
+++ b/drivers/net/failsafe/failsafe_intr.c
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2018 Mellanox Technologies, Ltd.
+ */
+
+/**
+ * @file
+ * Interrupts handling for failsafe driver.
+ */
+
+#include <unistd.h>
+
+#include "failsafe_private.h"
+
+/**
+ * Uninstall failsafe interrupt vector.
+ *
+ * @param priv
+ *   Pointer to failsafe private structure.
+ */
+static void
+fs_rx_intr_vec_uninstall(struct fs_priv *priv)
+{
+       struct rte_intr_handle *intr_handle;
+
+       intr_handle = &priv->intr_handle;
+       if (intr_handle->intr_vec != NULL) {
+               free(intr_handle->intr_vec);
+               intr_handle->intr_vec = NULL;
+       }
+       intr_handle->nb_efd = 0;
+}
+
+/**
+ * Installs failsafe interrupt vector to be registered with EAL later on.
+ *
+ * @param priv
+ *   Pointer to failsafe private structure.
+ *
+ * @return
+ *   0 on success, negative errno value otherwise and rte_errno is set.
+ */
+static int
+fs_rx_intr_vec_install(struct fs_priv *priv)
+{
+       unsigned int i;
+       unsigned int rxqs_n;
+       unsigned int n;
+       unsigned int count;
+       struct rte_intr_handle *intr_handle;
+
+       rxqs_n = priv->dev->data->nb_rx_queues;
+       n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
+       count = 0;
+       intr_handle = &priv->intr_handle;
+       RTE_ASSERT(intr_handle->intr_vec == NULL);
+       /* Allocate the interrupt vector of the failsafe Rx proxy interrupts */
+       intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
+       if (intr_handle->intr_vec == NULL) {
+               fs_rx_intr_vec_uninstall(priv);
+               rte_errno = ENOMEM;
+               ERROR("Failed to allocate memory for interrupt vector,"
+                     " Rx interrupts will not be supported");
+               return -rte_errno;
+       }
+       for (i = 0; i < n; i++) {
+               struct rxq *rxq = priv->dev->data->rx_queues[i];
+
+               /* Skip queues that cannot request interrupts. */
+               if (rxq == NULL || rxq->event_fd < 0) {
+                       /* Use invalid intr_vec[] index to disable entry. */
+                       intr_handle->intr_vec[i] =
+                               RTE_INTR_VEC_RXTX_OFFSET +
+                               RTE_MAX_RXTX_INTR_VEC_ID;
+                       continue;
+               }
+               if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
+                       rte_errno = E2BIG;
+                       ERROR("Too many Rx queues for interrupt vector size"
+                             " (%d), Rx interrupts cannot be enabled",
+                             RTE_MAX_RXTX_INTR_VEC_ID);
+                       fs_rx_intr_vec_uninstall(priv);
+                       return -rte_errno;
+               }
+               intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
+               intr_handle->efds[count] = rxq->event_fd;
+               count++;
+       }
+       if (count == 0) {
+               fs_rx_intr_vec_uninstall(priv);
+       } else {
+               intr_handle->nb_efd = count;
+               intr_handle->efd_counter_size = sizeof(uint64_t);
+       }
+       return 0;
+}
+
+
+/**
+ * Uninstall failsafe Rx interrupts subsystem.
+ *
+ * @param priv
+ *   Pointer to private structure.
+ *
+ * @return
+ *   0 on success, negative errno value otherwise and rte_errno is set.
+ */
+void
+failsafe_rx_intr_uninstall(struct rte_eth_dev *dev)
+{
+       fs_rx_intr_vec_uninstall(PRIV(dev));
+       dev->intr_handle = NULL;
+}
+
+/**
+ * Install failsafe Rx interrupts subsystem.
+ *
+ * @param priv
+ *   Pointer to private structure.
+ *
+ * @return
+ *   0 on success, negative errno value otherwise and rte_errno is set.
+ */
+int
+failsafe_rx_intr_install(struct rte_eth_dev *dev)
+{
+       struct fs_priv *priv = PRIV(dev);
+       const struct rte_intr_conf *const intr_conf =
+                       &priv->dev->data->dev_conf.intr_conf;
+
+       if (intr_conf->rxq == 0)
+               return 0;
+       if (fs_rx_intr_vec_install(priv) < 0)
+               return -rte_errno;
+       dev->intr_handle = &priv->intr_handle;
+       return 0;
+}

diff --git a/drivers/net/failsafe/failsafe_ops.c b/drivers/net/failsafe/failsafe_ops.c
index 946ac98f9c0c09fa2c994f9e53e39dd4ca59dde2..5cbc59157e8039627ec2534513a142600785b43e 100644 (file)
--- a/drivers/net/failsafe/failsafe_ops.c
+++ b/drivers/net/failsafe/failsafe_ops.c
@@ -33,6 +33,7 @@
 
 #include <stdbool.h>
 #include <stdint.h>
+#include <unistd.h>
 
 #include <rte_debug.h>
 #include <rte_atomic.h>
@@ -199,6 +200,9 @@ fs_dev_start(struct rte_eth_dev *dev)
        uint8_t i;
        int ret;
 
+       ret = failsafe_rx_intr_install(dev);
+       if (ret)
+               return ret;
        FOREACH_SUBDEV(sdev, i, dev) {
                if (sdev->state != DEV_ACTIVE)
                        continue;
@@ -228,6 +232,7 @@ fs_dev_stop(struct rte_eth_dev *dev)
                rte_eth_dev_stop(PORT_ID(sdev));
                sdev->state = DEV_STARTED - 1;
        }
+       failsafe_rx_intr_uninstall(dev);
 }
 
 static int
@@ -317,6 +322,8 @@ fs_rx_queue_release(void *queue)
        if (queue == NULL)
                return;
        rxq = queue;
+       if (rxq->event_fd > 0)
+               close(rxq->event_fd);
        dev = rxq->priv->dev;
        FOREACH_SUBDEV_STATE(sdev, i, dev, DEV_ACTIVE)
                SUBOPS(sdev, rx_queue_release)
@@ -333,6 +340,16 @@ fs_rx_queue_setup(struct rte_eth_dev *dev,
                const struct rte_eth_rxconf *rx_conf,
                struct rte_mempool *mb_pool)
 {
+       /*
+        * FIXME: Add a proper interface in rte_eal_interrupts for
+        * allocating eventfd as an interrupt vector.
+        * For the time being, fake as if we are using MSIX interrupts,
+        * this will cause rte_intr_efd_enable to allocate an eventfd for us.
+        */
+       struct rte_intr_handle intr_handle = {
+               .type = RTE_INTR_HANDLE_VFIO_MSIX,
+               .efds = { -1, },
+       };
        struct sub_device *sdev;
        struct rxq *rxq;
        uint8_t i;
@@ -370,6 +387,10 @@ fs_rx_queue_setup(struct rte_eth_dev *dev,
        rxq->info.nb_desc = nb_rx_desc;
        rxq->priv = PRIV(dev);
        rxq->sdev = PRIV(dev)->subs;
+       ret = rte_intr_efd_enable(&intr_handle, 1);
+       if (ret < 0)
+               return ret;
+       rxq->event_fd = intr_handle.efds[0];
        dev->data->rx_queues[rx_queue_id] = rxq;
        FOREACH_SUBDEV_STATE(sdev, i, dev, DEV_ACTIVE) {
                ret = rte_eth_rx_queue_setup(PORT_ID(sdev),
@@ -387,6 +408,46 @@ free_rxq:
        return ret;
 }
 
+static int
+fs_rx_intr_enable(struct rte_eth_dev *dev, uint16_t idx)
+{
+       struct rxq *rxq;
+
+       if (idx >= dev->data->nb_rx_queues) {
+               rte_errno = EINVAL;
+               return -rte_errno;
+       }
+       rxq = dev->data->rx_queues[idx];
+       if (rxq == NULL || rxq->event_fd <= 0) {
+               rte_errno = EINVAL;
+               return -rte_errno;
+       }
+       rxq->enable_events = 1;
+       return 0;
+}
+
+static int
+fs_rx_intr_disable(struct rte_eth_dev *dev, uint16_t idx)
+{
+       struct rxq *rxq;
+       uint64_t u64;
+
+       if (idx >= dev->data->nb_rx_queues) {
+               rte_errno = EINVAL;
+               return -rte_errno;
+       }
+       rxq = dev->data->rx_queues[idx];
+       if (rxq == NULL || rxq->event_fd <= 0) {
+               rte_errno = EINVAL;
+               return -rte_errno;
+       }
+       rxq->enable_events = 0;
+       /* Clear pending events */
+       while (read(rxq->event_fd, &u64, sizeof(uint64_t)) >  0)
+               ;
+       return 0;
+}
+
 static bool
 fs_txq_offloads_valid(struct rte_eth_dev *dev, uint64_t offloads)
 {
@@ -888,6 +949,8 @@ const struct eth_dev_ops failsafe_ops = {
        .tx_queue_setup = fs_tx_queue_setup,
        .rx_queue_release = fs_rx_queue_release,
        .tx_queue_release = fs_tx_queue_release,
+       .rx_queue_intr_enable = fs_rx_intr_enable,
+       .rx_queue_intr_disable = fs_rx_intr_disable,
        .flow_ctrl_get = fs_flow_ctrl_get,
        .flow_ctrl_set = fs_flow_ctrl_set,
        .mac_addr_remove = fs_mac_addr_remove,

diff --git a/drivers/net/failsafe/failsafe_private.h b/drivers/net/failsafe/failsafe_private.h
index 7754248ff827f7d81b510d403bdddb761699bb87..419e5e7d1058b5db55b0f440ca764a4d869e54a4 100644 (file)
--- a/drivers/net/failsafe/failsafe_private.h
+++ b/drivers/net/failsafe/failsafe_private.h
@@ -40,6 +40,7 @@
 #include <rte_dev.h>
 #include <rte_ethdev_driver.h>
 #include <rte_devargs.h>
+#include <rte_interrupts.h>
 
 #define FAILSAFE_DRIVER_NAME "Fail-safe PMD"
 
@@ -68,6 +69,8 @@ struct rxq {
        /* next sub_device to poll */
        struct sub_device *sdev;
        unsigned int socket_id;
+       int event_fd;
+       unsigned int enable_events:1;
        struct rte_eth_rxq_info info;
        rte_atomic64_t refcnt[];
 };
@@ -145,6 +148,7 @@ struct fs_priv {
        uint32_t mac_addr_pool[FAILSAFE_MAX_ETHADDR];
        /* current capabilities */
        struct rte_eth_dev_info infos;
+       struct rte_intr_handle intr_handle; /* Port interrupt handle. */
        /*
         * Fail-safe state machine.
         * This level will be tracking state of the EAL and eth
@@ -159,6 +163,11 @@ struct fs_priv {
        int flow_isolated:1;
 };
 
+/* FAILSAFE_INTR */
+
+int failsafe_rx_intr_install(struct rte_eth_dev *dev);
+void failsafe_rx_intr_uninstall(struct rte_eth_dev *dev);
+
 /* MISC */
 
 int failsafe_hotplug_alarm_install(struct rte_eth_dev *dev);