]> git.droids-corp.org - dpdk.git/commitdiff
lib: fix shifting 32-bit signed variable 31 times
authorFerruh Yigit <ferruh.yigit@intel.com>
Sun, 28 Oct 2018 01:08:44 +0000 (01:08 +0000)
committerThomas Monjalon <thomas@monjalon.net>
Tue, 6 Nov 2018 00:14:05 +0000 (01:14 +0100)
Fix cppcheck warning by marking variable as unsigned.

Fixes: dc276b5780c2 ("acl: new library")
Fixes: 986ff526fb84 ("net: add CRC computation API")
Cc: stable@dpdk.org
Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
lib/librte_acl/acl_gen.c
lib/librte_net/rte_net_crc.c

index bed66be08a0a3aaf9b60d7cc6b7755dc2fe3a913..35a0140b4c401e7d0770fadb3ad7753fe87e7d2c 100644 (file)
@@ -163,7 +163,7 @@ acl_count_sequential_groups(struct rte_acl_bitset *bits, int zero_one)
 
        for (n = QRANGE_MIN; n < UINT8_MAX + 1; n++) {
                if (bits->bits[n / (sizeof(bits_t) * 8)] &
-                               (1 << (n % (sizeof(bits_t) * 8)))) {
+                               (1U << (n % (sizeof(bits_t) * 8)))) {
                        if (zero_one == 1 && last_bit != 1)
                                ranges++;
                        last_bit = 1;
index 73ac3a9591fb27d696193d47317459636840bc19..dca0830e2c3db58a58e7f3019b8075278f3419cb 100644 (file)
@@ -69,8 +69,8 @@ reflect_32bits(uint32_t val)
        uint32_t i, res = 0;
 
        for (i = 0; i < 32; i++)
-               if ((val & (1 << i)) != 0)
-                       res |= (uint32_t)(1 << (31 - i));
+               if ((val & (1U << i)) != 0)
+                       res |= (uint32_t)(1U << (31 - i));
 
        return res;
 }