extern "C" {
#endif
+#define EF10_TXQ_MINNDESCS 512
/* Number of hardware PIO buffers (for compile-time resource dimensions) */
#define EF10_MAX_PIOBUF_NBUFS (16)
uint32_t enc_txq_limit;
uint32_t enc_rxq_limit;
uint32_t enc_txq_max_ndescs;
+ uint32_t enc_txq_min_ndescs;
uint32_t enc_buftbl_limit;
uint32_t enc_piobuf_limit;
uint32_t enc_piobuf_size;
efx_tx_fini(
__in efx_nic_t *enp);
+/*
+ * This symbol is deprecated and will be removed.
+ * Use the field from efx_nic_cfg_t instead.
+ */
#define EFX_TXQ_MINNDESCS 512
#define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
EFSYS_ASSERT3U(label, <, EFX_EV_TX_NLABELS);
EFSYS_ASSERT(ISP2(encp->enc_txq_max_ndescs));
- EFX_STATIC_ASSERT(ISP2(EFX_TXQ_MINNDESCS));
+ EFSYS_ASSERT(ISP2(encp->enc_txq_min_ndescs));
if (!ISP2(ndescs) ||
- (ndescs < EFX_TXQ_MINNDESCS) ||
+ (ndescs < encp->enc_txq_min_ndescs) ||
(ndescs > encp->enc_txq_max_ndescs)) {
rc = EINVAL;
goto fail1;
goto fail2;
}
for (size = 0;
- (1 << size) <= (int)(encp->enc_txq_max_ndescs / EFX_TXQ_MINNDESCS);
+ (1U << size) <= encp->enc_txq_max_ndescs / encp->enc_txq_min_ndescs;
size++)
- if ((1 << size) == (int)(ndescs / EFX_TXQ_MINNDESCS))
+ if ((1U << size) == (uint32_t)ndescs / encp->enc_txq_min_ndescs)
break;
if (id + (1 << size) >= encp->enc_buftbl_limit) {
rc = EINVAL;
* descriptor writes, preventing the use of 4096 descriptor TXQs.
*/
encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096;
+ encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS;
EFX_STATIC_ASSERT(HUNT_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
* stuffing.
*/
encp->enc_txq_max_ndescs = 2048;
+ encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS;
EFX_STATIC_ASSERT(MEDFORD2_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
encp->enc_piobuf_limit = MEDFORD2_PIOBUF_NBUFS;
* stuffing.
*/
encp->enc_txq_max_ndescs = 2048;
+ encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS;
EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
#endif
#define EFX_TXQ_DC_NDESCS(_dcsize) (8 << (_dcsize))
+#define SIENA_TXQ_MAXNDESCS 4096
+#define SIENA_TXQ_MINNDESCS 512
+
#define SIENA_NVRAM_CHUNK 0x80
encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq);
encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq);
- encp->enc_txq_max_ndescs = 4096;
+ encp->enc_txq_max_ndescs = SIENA_TXQ_MAXNDESCS;
+ encp->enc_txq_min_ndescs = SIENA_TXQ_MINNDESCS;
encp->enc_buftbl_limit = SIENA_SRAM_ROWS -
(encp->enc_txq_limit * EFX_TXQ_DC_NDESCS(EFX_TXQ_DC_SIZE)) -