/* enforce 512B alignment on default Rx DMA addresses */
#define MBUF_DMA_ADDR_DEFAULT(mb) \
- ((uint64_t) RTE_ALIGN(((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM), 512))
+ ((uint64_t) RTE_ALIGN(((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM),\
+ FM10K_RX_DATABUF_ALIGN))
static inline void fifo_reset(struct fifo *fifo, uint32_t len)
{
uint64_t boundary1, boundary2;
/* 512B aligned? */
- if (RTE_ALIGN(addr, 512) == addr)
+ if (RTE_ALIGN(addr, FM10K_RX_DATABUF_ALIGN) == addr)
return 1;
/* 8B aligned, and max Ethernet frame would not cross a 4KB boundary? */
#include "fm10k.h"
#include "base/fm10k_api.h"
-#define FM10K_RX_BUFF_ALIGN 512
/* Default delay to acquire mailbox lock */
#define FM10K_MBXLOCK_DELAY_US 20
#define UINT64_LOWER_32BITS_MASK 0x00000000ffffffffULL
/* Configure the Rx buffer size for one buff without split */
buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
RTE_PKTMBUF_HEADROOM);
+ /* As RX buffer is aligned to 512B within mbuf, some bytes are
+ * reserved for this purpose, and the worst case could be 511B.
+ * But SRR reg assumes all buffers have the same size. In order
+ * to fill the gap, we'll have to consider the worst case and
+ * assume 512B is reserved. If we don't do so, it's possible
+ * for HW to overwrite data to next mbuf.
+ */
+ buf_size -= FM10K_RX_DATABUF_ALIGN;
+
FM10K_WRITE_REG(hw, FM10K_SRRCTL(i),
buf_size >> FM10K_SRRCTL_BSIZEPKT_SHIFT);
RTE_PKTMBUF_HEADROOM;
/* account for up to 512B of alignment */
- min_size -= FM10K_RX_BUFF_ALIGN;
+ min_size -= FM10K_RX_DATABUF_ALIGN;
/* sanity check for overflow */
if (min_size > mp->elt_size)