asm volatile ("pld [%0]" : : "r" (p));
}
+static inline void rte_prefetch_non_temporal(const volatile void *p)
+{
+ /* non-temporal version not available, fallback to rte_prefetch0 */
+ rte_prefetch0(p);
+}
+
#ifdef __cplusplus
}
#endif
asm volatile ("PRFM PLDL3KEEP, [%0]" : : "r" (p));
}
+static inline void rte_prefetch_non_temporal(const volatile void *p)
+{
+ asm volatile ("PRFM PLDL1STRM, [%0]" : : "r" (p));
+}
+
#ifdef __cplusplus
}
#endif
asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p));
}
+static inline void rte_prefetch_non_temporal(const volatile void *p)
+{
+ /* non-temporal version not available, fallback to rte_prefetch0 */
+ rte_prefetch0(p);
+}
+
#ifdef __cplusplus
}
#endif
__builtin_prefetch((const void *)(uintptr_t)p, 0, 1);
}
+static inline void rte_prefetch_non_temporal(const volatile void *p)
+{
+ /* non-temporal version not available, fallback to rte_prefetch0 */
+ rte_prefetch0(p);
+}
+
#ifdef __cplusplus
}
#endif
asm volatile ("prefetcht2 %[p]" : : [p] "m" (*(const volatile char *)p));
}
+static inline void rte_prefetch_non_temporal(const volatile void *p)
+{
+ asm volatile ("prefetchnta %[p]" : : [p] "m" (*(const volatile char *)p));
+}
+
#ifdef __cplusplus
}
#endif
*/
static inline void rte_prefetch2(const volatile void *p);
+/**
+ * Prefetch a cache line into all cache levels (non-temporal/transient version)
+ *
+ * The non-temporal prefetch is intended as a prefetch hint that processor will
+ * use the prefetched data only once or short period, unlike the
+ * rte_prefetch0() function which imply that prefetched data to use repeatedly.
+ *
+ * @param p
+ * Address to prefetch
+ */
+static inline void rte_prefetch_non_temporal(const volatile void *p);
+
#endif /* _RTE_PREFETCH_H_ */