TEST_CASE_ST(ut_setup, ut_teardown,
test_AES_CBC_HMAC_SHA1_encrypt_digest_sessionless),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_CTR_encrypt_digest_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_CTR_encrypt_digest_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_CTR_encrypt_digest_case_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_CTR_digest_verify_decrypt_case_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_CTR_digest_verify_decrypt_case_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_CTR_digest_verify_decrypt_case_3),
+
TEST_CASE_ST(ut_setup, ut_teardown,
test_not_in_place_crypto),
* RTE_CRYPTO_SYM_CIPHER_AES128_CBC
* RTE_CRYPTO_SYM_CIPHER_AES192_CBC
* RTE_CRYPTO_SYM_CIPHER_AES256_CBC
+* RTE_CRYPTO_SYM_CIPHER_AES128_CTR
+* RTE_CRYPTO_SYM_CIPHER_AES192_CTR
+* RTE_CRYPTO_SYM_CIPHER_AES256_CTR
Hash algorithms:
* Dropped specific Xen Dom0 code.
* Dropped specific anonymous mempool code in testpmd.
+* **Added AES-CTR support to AESNI MB PMD.**
+
+ Now AESNI MB PMD supports 128/192/256-bit counter mode AES encryption and
+ decryption.
+
* **Added support of AES counter mode for Intel QuickAssist devices.**
Enabled support for the AES CTR algorithm for Intel QuickAssist devices.
}, }
}, }
},
+ { /* AES CTR */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_AES_CTR,
+ .block_size = 16,
+ .key_size = {
+ .min = 16,
+ .max = 32,
+ .increment = 8
+ },
+ .iv_size = {
+ .min = 16,
+ .max = 16,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
};