net/mlx5: fix software parsing support query

Currently, the PMD decides if the software parsing
offload can enable outer IPv4 checksum and tunneled
TSO support by checking config->hw_csum and config->tso
respectively.

This is incorrect, the right way is to check the following
flags returned by the mlx5dv_query_device function:

MLX5DV_SW_PARSING - check general swp support.
MLX5DV_SW_PARSING_CSUM - check swp checksum support.
MLX5DV_SW_PARSING_LSO - check swp LSO/TSO support.

The fix enables the offloads according to the correct
flags returned by the kernel.

Fixes: e46821e9fcdc ("net/mlx5: separate generic tunnel TSO from the standard one")
Cc: stable@dpdk.org
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Tested-by: Idan Hackmon <idanhac@nvidia.com>

diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c
index 0dcf5000e91e2fce1da5f5911a2117255d6338e3..e08082ed70e465260366592082a66b1ecfa0509e 100644 (file)
--- a/drivers/net/mlx5/linux/mlx5_os.c
+++ b/drivers/net/mlx5/linux/mlx5_os.c
@@ -1111,7 +1111,8 @@ err_secondary:
                swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
        DRV_LOG(DEBUG, "SWP support: %u", swp);
 #endif
-       config->swp = !!swp;
+       config->swp = swp & (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP |
+               MLX5_SW_PARSING_TSO_CAP);
 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
        if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
                struct mlx5dv_striding_rq_caps mprq_caps =

diff --git a/drivers/net/mlx5/linux/mlx5_os.h b/drivers/net/mlx5/linux/mlx5_os.h
index 2991d37df2543e5a735d8c1884b82e9baf749d23..da036edb72ccfa947daa36c75f9a4d9334b35b1a 100644 (file)
--- a/drivers/net/mlx5/linux/mlx5_os.h
+++ b/drivers/net/mlx5/linux/mlx5_os.h
@@ -21,4 +21,16 @@ enum {
 
 int mlx5_auxiliary_get_ifindex(const char *sf_name);
 
+
+enum mlx5_sw_parsing_offloads {
+#ifdef HAVE_IBV_MLX5_MOD_SWP
+       MLX5_SW_PARSING_CAP      = MLX5DV_SW_PARSING,
+       MLX5_SW_PARSING_CSUM_CAP = MLX5DV_SW_PARSING_CSUM,
+       MLX5_SW_PARSING_TSO_CAP  = MLX5DV_SW_PARSING_LSO,
+#else
+       MLX5_SW_PARSING_CAP      = 0,
+       MLX5_SW_PARSING_CSUM_CAP = 0,
+       MLX5_SW_PARSING_TSO_CAP  = 0,
+#endif
+};
 #endif /* RTE_PMD_MLX5_OS_H_ */

diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 6811b8bd35fdae8e6019325ecbcf521891568b2e..d74ac19cf82329bd05aa49c891d395400c9f268e 100644 (file)
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -267,7 +267,7 @@ struct mlx5_dev_config {
        unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
        unsigned int lacp_by_user:1;
        /* Enable user to manage LACP traffic. */
-       unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
+       unsigned int swp:3; /* Tx generic tunnel checksum and TSO offload. */
        unsigned int devx:1; /* Whether devx interface is available or not. */
        unsigned int dest_tir:1; /* Whether advanced DR API is available. */
        unsigned int reclaim_mode:2; /* Memory reclaim mode. */

diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index 92fbdab56895b9934bcf173a4722d0153057cacc..eb2636782723b18694ac6ba2de4c01e1863bbf54 100644 (file)
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -111,9 +111,9 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
        if (config->tx_pp)
                offloads |= DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP;
        if (config->swp) {
-               if (config->hw_csum)
+               if (config->swp & MLX5_SW_PARSING_CSUM_CAP)
                        offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
-               if (config->tso)
+               if (config->swp & MLX5_SW_PARSING_TSO_CAP)
                        offloads |= (DEV_TX_OFFLOAD_IP_TNL_TSO |
                                     DEV_TX_OFFLOAD_UDP_TNL_TSO);
        }
@@ -972,10 +972,13 @@ txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
                txq_ctrl->txq.tso_en = 1;
        }
        txq_ctrl->txq.tunnel_en = config->tunnel_en | config->swp;
-       txq_ctrl->txq.swp_en = ((DEV_TX_OFFLOAD_IP_TNL_TSO |
-                                DEV_TX_OFFLOAD_UDP_TNL_TSO |
-                                DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) &
-                               txq_ctrl->txq.offloads) && config->swp;
+       txq_ctrl->txq.swp_en = (((DEV_TX_OFFLOAD_IP_TNL_TSO |
+                                 DEV_TX_OFFLOAD_UDP_TNL_TSO) &
+                                 txq_ctrl->txq.offloads) && (config->swp &
+                                 MLX5_SW_PARSING_TSO_CAP)) |
+                               ((DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM &
+                                txq_ctrl->txq.offloads) && (config->swp &
+                                MLX5_SW_PARSING_CSUM_CAP));
 }
 
 /**