common/mlx5: add DevX attributes for compress
authorMatan Azrad <matan@nvidia.com>
Wed, 20 Jan 2021 11:29:25 +0000 (11:29 +0000)
committerAkhil Goyal <akhil.goyal@nxp.com>
Wed, 27 Jan 2021 19:40:03 +0000 (20:40 +0100)
Add the DevX attributes for compress related engines:
- compress
- decompress
- dma

Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
drivers/common/mlx5/mlx5_devx_cmds.c
drivers/common/mlx5/mlx5_devx_cmds.h
drivers/common/mlx5/mlx5_prm.h

index d5859c2..33acd73 100644 (file)
@@ -732,6 +732,16 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
        attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
        attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
        attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
+       attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo);
+       attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress);
+       attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress);
+       attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
+                                                compress_min_block_size);
+       attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);
+       attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,
+                                             log_compress_mmo_size);
+       attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,
+                                               log_decompress_mmo_size);
        if (attr->qos.sup) {
                MLX5_SET(query_hca_cap_in, in, op_mod,
                         MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
index bf83a90..696a981 100644 (file)
@@ -130,6 +130,13 @@ struct mlx5_hca_attr {
        uint32_t log_max_srq;
        uint32_t log_max_srq_sz;
        uint32_t rss_ind_tbl_cap;
+       uint32_t mmo_dma_en:1;
+       uint32_t mmo_compress_en:1;
+       uint32_t mmo_decompress_en:1;
+       uint32_t compress_min_block_size:4;
+       uint32_t log_max_mmo_dma:5;
+       uint32_t log_max_mmo_compress:5;
+       uint32_t log_max_mmo_decompress:5;
 };
 
 struct mlx5_devx_wq_attr {
index c9eba22..c4702ed 100644 (file)
@@ -1127,7 +1127,15 @@ enum {
 struct mlx5_ifc_cmd_hca_cap_bits {
        u8 reserved_at_0[0x30];
        u8 vhca_id[0x10];
-       u8 reserved_at_40[0x40];
+       u8 reserved_at_40[0x20];
+       u8 reserved_at_60[0x3];
+       u8 log_regexp_scatter_gather_size[0x5];
+       u8 reserved_at_68[0x3];
+       u8 log_dma_mmo_size[0x5];
+       u8 reserved_at_70[0x3];
+       u8 log_compress_mmo_size[0x5];
+       u8 reserved_at_78[0x3];
+       u8 log_decompress_mmo_size[0x5];
        u8 log_max_srq_sz[0x8];
        u8 log_max_qp_sz[0x8];
        u8 reserved_at_90[0x9];
@@ -1175,7 +1183,13 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8 log_max_ra_res_dc[0x6];
        u8 reserved_at_140[0xa];
        u8 log_max_ra_req_qp[0x6];
-       u8 reserved_at_150[0xa];
+       u8 rtr2rts_qp_counters_set_id[0x1];
+       u8 rts2rts_udp_sport[0x1];
+       u8 rts2rts_lag_tx_port_affinity[0x1];
+       u8 dma_mmo[0x1];
+       u8 compress_min_block_size[0x4];
+       u8 compress[0x1];
+       u8 decompress[0x1];
        u8 log_max_ra_res_qp[0x6];
        u8 end_pad[0x1];
        u8 cc_query_allowed[0x1];