Add the needed fields for virtq DevX object to read the error state.
Acked-by: Matan Azrad <matan@nvidia.com>
Signed-off-by: Xueming Li <xuemingl@nvidia.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
        attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
                                              hw_available_index);
        attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
+       attr->state = MLX5_GET16(virtio_net_q, virtq, state);
+       attr->error_type = MLX5_GET16(virtio_net_q, virtq,
+                                     virtio_q_context.error_type);
        return ret;
 }
 
 
                uint32_t size;
                uint64_t offset;
        } umems[3];
+       uint8_t error_type;
 };
 
 
 
        u8 used_addr[0x40];
        u8 available_addr[0x40];
        u8 virtio_q_mkey[0x20];
-       u8 reserved_at_160[0x20];
+       u8 reserved_at_160[0x18];
+       u8 error_type[0x8];
        u8 umem_1_id[0x20];
        u8 umem_1_size[0x20];
        u8 umem_1_offset[0x40];
        u8 vhost_log_page[0x5];
        u8 reserved_at_90[0xc];
        u8 state[0x4];
-       u8 error_type[0x8];
+       u8 reserved_at_a0[0x8];
        u8 tisn_or_qpn[0x18];
        u8 dirty_bitmap_mkey[0x20];
        u8 dirty_bitmap_size[0x20];
        struct mlx5_ifc_virtio_net_q_bits virtq;
 };
 
+enum {
+       MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27,
+};
+
 enum {
        MLX5_QP_ST_RC = 0x0,
 };