net/mlx5: fix hairpin dependency on destination DevX TIR

The PMD supports hairpin only if DevX is supported and DV flow is
enabled.

When destination DevX TIR is not supported, the PMD tries to create TIR
action, and fails.

Avoid supporting hairpin when destination DevX TIR is not supported.

Fixes: b6b3bf86bd1a ("net/mlx5: get hairpin capabilities")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c
index cefb45064eeae56765c913e721151475b4ee2eda..a7924b103ca7726767524be67dac0a84c4906a28 100644 (file)
--- a/drivers/net/mlx5/mlx5_ethdev.c
+++ b/drivers/net/mlx5/mlx5_ethdev.c
@@ -569,12 +569,12 @@ mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev)
  *   0 on success, a negative errno value otherwise and rte_errno is set.
  */
 int
-mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
-                        struct rte_eth_hairpin_cap *cap)
+mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap)
 {
        struct mlx5_priv *priv = dev->data->dev_private;
+       struct mlx5_dev_config *config = &priv->config;
 
-       if (priv->sh->devx == 0) {
+       if (!priv->sh->devx || !config->dest_tir || !config->dv_flow_en) {
                rte_errno = ENOTSUP;
                return -rte_errno;
        }