ixgbe/base: x540 changes

Signed-off-by: Jijiang Liu <jijiang.liu@intel.com>
Acked-by: Helin Zhang <helin.zhang@intel.com>
Tested-by: Waterman Cao <waterman.cao@intel.com>
[Thomas: split code drop]

diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
index 564aa7b..06b1c7d 100644 (file)
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
@@ -1947,6 +1947,18 @@ enum {
 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC     0x0 /* Alt SAN MAC exists */
 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN     0x1 /* Alt WWN base exists */
 
+/* FW header offset */
+#define IXGBE_X540_FW_PASSTHROUGH_PATCH_CONFIG_PTR     0x4
+#define IXGBE_X540_FW_MODULE_MASK                      0x7FFF
+/* 4KB multiplier */
+#define IXGBE_X540_FW_MODULE_LENGTH                    0x1000
+/* version word 2 (month & day) */
+#define IXGBE_X540_FW_PATCH_VERSION_2          0x5
+/* version word 3 (silicon compatibility & year) */
+#define IXGBE_X540_FW_PATCH_VERSION_3          0x6
+/* version word 4 (major & minor numbers) */
+#define IXGBE_X540_FW_PATCH_VERSION_4          0x7
+
 #define IXGBE_DEVICE_CAPS_WOL_PORT0_1  0x4 /* WoL supported on ports 0 & 1 */
 #define IXGBE_DEVICE_CAPS_WOL_PORT0    0x8 /* WoL supported on port 0 */
 #define IXGBE_DEVICE_CAPS_WOL_MASK     0xC /* Mask for WoL capabilities */

diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c
index 1610f6c..2738f3d 100644 (file)
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c
@@ -44,7 +44,6 @@ POSSIBILITY OF SUCH DAMAGE.
 #define IXGBE_X540_VFT_TBL_SIZE                128
 #define IXGBE_X540_RX_PB_SIZE          384
 
-STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
@@ -479,12 +478,13 @@ s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
  **/
 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
 {
-       u16 i;
-       u16 j;
+       u16 i, j;
        u16 checksum = 0;
        u16 length = 0;
        u16 pointer = 0;
        u16 word = 0;
+       u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM;
+       u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
 
        /*
         * Do not use hw->eeprom.ops.read because we do not want to take
@@ -495,19 +495,20 @@ u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
        DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
 
        /* Include 0x0-0x3F in the checksum */
-       for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
+       for (i = 0; i <= checksum_last_word; i++) {
                if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) {
                        DEBUGOUT("EEPROM read failed\n");
                        break;
                }
-               checksum += word;
+               if (i != IXGBE_EEPROM_CHECKSUM)
+                       checksum += word;
        }
 
        /*
         * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
         * FW, PHY module, and PCIe Expansion/Option ROM pointers.
         */
-       for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
+       for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
                if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
                        continue;
 
@@ -631,8 +632,10 @@ s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
         */
        status = hw->eeprom.ops.read(hw, 0, &checksum);
 
-       if (status != IXGBE_SUCCESS)
+       if (status != IXGBE_SUCCESS) {
                DEBUGOUT("EEPROM read failed\n");
+               return status;
+       }
 
        if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
            IXGBE_SUCCESS) {
@@ -641,7 +644,7 @@ s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
                /*
                 * Do not use hw->eeprom.ops.write because we do not want to
                 * take the synchronization semaphores twice here.
-               */
+                */
                status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
                                                  checksum);
 
@@ -662,7 +665,7 @@ s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
  *  Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
  *  EEPROM from shadow RAM to the flash device.
  **/
-STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
+s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
 {
        u32 flup;
        s32 status;
@@ -684,7 +687,7 @@ STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
        else
                DEBUGOUT("Flash update time out\n");
 
-       if (hw->revision_id == 0) {
+       if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) {
                flup = IXGBE_READ_REG(hw, IXGBE_EEC);
 
                if (flup & IXGBE_EEC_SEC1VAL) {

diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.h
index 8a10dd4..31215f0 100644 (file)
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.h
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.h
@@ -56,6 +56,7 @@ s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, u16 offset, u16 words,
 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw);
 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, u16 *checksum_val);
 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw);
+s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
 
 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);