With the above configuration, each send queue's decscriptor buffer count is
limited to a maximum of 64 buffers.
-- ``switch header enable`` (default ``none``)
+- ``Switch header enable`` (default ``none``)
A port can be configured to a specific switch header type by using
``switch_header`` ``devargs`` parameter.
traffic on this port should be higig2 traffic only. Supported switch header
types are "higig2" and "dsa".
+- ``RSS tag as XOR`` (default ``0``)
+
+ C0 HW revision onward, The HW gives an option to configure the RSS adder as
+
+ * ``rss_adder<7:0> = flow_tag<7:0> ^ flow_tag<15:8> ^ flow_tag<23:16> ^ flow_tag<31:24>``
+
+ * ``rss_adder<7:0> = flow_tag<7:0>``
+
+ Latter one aligns with standard NIC behavior vs former one is a legacy
+ RSS adder scheme used in OCTEON TX2 products.
+
+ By default, the driver runs in the latter mode from C0 HW revision onward.
+ Setting this flag to 1 to select the legacy mode.
+
+ For example to select the legacy mode(RSS tag adder as XOR)::
+ -w 0002:02:00.0,tag_as_xor=1
+
.. note::
Above devarg parameters are configurable per device, user needs to pass the
#define OTX2_MBOX_RSP_SIG (0xbeef)
/* Signature, for validating corrupted msgs */
uint16_t __otx2_io sig;
-#define OTX2_MBOX_VERSION (0x0003)
+#define OTX2_MBOX_VERSION (0x0004)
/* Version of msg's structure for this ID */
uint16_t __otx2_io ver;
/* Offset of next msg within mailbox region */
uint16_t __otx2_io sso_func;
uint64_t __otx2_io rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
uint64_t __otx2_io way_mask;
+#define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
+ uint64_t flags;
};
struct nix_lf_alloc_rsp {
req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
}
req->rx_cfg |= BIT_ULL(32 /* DROP_RE */);
+ if (dev->rss_tag_as_xor == 0)
+ req->flags = NIX_LF_RSS_TAG_LSB_AS_ADDER;
rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
if (rc)
uintptr_t base;
uintptr_t lmt_addr;
uint16_t scalar_ena;
+ uint16_t rss_tag_as_xor;
uint16_t max_sqb_count;
uint16_t rx_offload_flags; /* Selected Rx offload flags(NIX_RX_*_F) */
uint64_t rx_offloads;
#define OTX2_FLOW_PREALLOC_SIZE "flow_prealloc_size"
#define OTX2_FLOW_MAX_PRIORITY "flow_max_priority"
#define OTX2_SWITCH_HEADER_TYPE "switch_header"
+#define OTX2_RSS_TAG_AS_XOR "tag_as_xor"
int
otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev)
uint16_t switch_header_type = 0;
uint16_t flow_max_priority = 3;
uint16_t scalar_enable = 0;
+ uint16_t rss_tag_as_xor = 0;
struct rte_kvargs *kvlist;
if (devargs == NULL)
&parse_flow_max_priority, &flow_max_priority);
rte_kvargs_process(kvlist, OTX2_SWITCH_HEADER_TYPE,
&parse_switch_header_type, &switch_header_type);
+ rte_kvargs_process(kvlist, OTX2_RSS_TAG_AS_XOR,
+ &parse_flag, &rss_tag_as_xor);
rte_kvargs_free(kvlist);
null_devargs:
dev->scalar_ena = scalar_enable;
+ dev->rss_tag_as_xor = rss_tag_as_xor;
dev->max_sqb_count = sqb_count;
dev->rss_info.rss_size = rss_size;
dev->npc_flow.flow_prealloc_size = flow_prealloc_size;
OTX2_MAX_SQB_COUNT "=<8-512>"
OTX2_FLOW_PREALLOC_SIZE "=<1-32>"
OTX2_FLOW_MAX_PRIORITY "=<1-32>"
- OTX2_SWITCH_HEADER_TYPE "=<higig2|dsa>");
+ OTX2_SWITCH_HEADER_TYPE "=<higig2|dsa>"
+ OTX2_RSS_TAG_AS_XOR "=1");