.opcode = IONIC_CMD_Q_INIT,
.type = q->type,
.index = q->index,
- .flags = IONIC_QINIT_F_SG,
+ .flags = IONIC_QINIT_F_SG | IONIC_QINIT_F_ENA,
.intr_index = cq->bound_intr->index,
.ring_size = rte_log2_u32(q->num_descs),
.ring_base = q->base_pa,
.opcode = IONIC_CMD_Q_INIT,
.type = q->type,
.index = q->index,
- .flags = IONIC_QINIT_F_SG,
+ .flags = IONIC_QINIT_F_SG | IONIC_QINIT_F_ENA,
.intr_index = cq->bound_intr->index,
.ring_size = rte_log2_u32(q->num_descs),
.ring_base = q->base_pa,
err = ionic_lif_txq_init(txq);
if (err)
return err;
+ } else {
+ ionic_qcq_enable(txq);
}
- ionic_qcq_enable(txq);
-
tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
return 0;
err = ionic_lif_rxq_init(rxq);
if (err)
return err;
+ } else {
+ ionic_qcq_enable(rxq);
}
/* Allocate buffers for descriptor rings */
return -1;
}
- ionic_qcq_enable(rxq);
-
rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
return 0;