/* SPDX-License-Identifier: BSD-3-Clause
*
- * Copyright 2017-2020 NXP
+ * Copyright 2017-2022 NXP
*
*/
#ifndef __RTE_DPAA_BUS_H__
uint32_t bman_idx; /**< BMAN Portal ID*/
uint32_t qman_idx; /**< QMAN Portal ID*/
struct dpaa_portal_dqrr dpaa_held_bufs;
- struct rte_crypto_op **dpaa_sec_ops;
- int dpaa_sec_op_nb;
uint64_t tid;/**< Parent Thread id for this portal */
};
RTE_PER_LCORE(dpaa_io)->dpaa_held_bufs.dqrr_held
#define DPAA_PER_LCORE_DQRR_MBUF(i) \
RTE_PER_LCORE(dpaa_io)->dpaa_held_bufs.mbuf[i]
-#define DPAA_PER_LCORE_RTE_CRYPTO_OP \
- RTE_PER_LCORE(dpaa_io)->dpaa_sec_ops
-#define DPAA_PER_LCORE_DPAA_SEC_OP_NB \
- RTE_PER_LCORE(dpaa_io)->dpaa_sec_op_nb
/* Various structures representing contiguous memory maps */
struct dpaa_memseg {
struct dpaa_sec_job *job;
struct dpaa_sec_op_ctx *ctx;
- if (DPAA_PER_LCORE_DPAA_SEC_OP_NB >= DPAA_SEC_BURST)
- return qman_cb_dqrr_defer;
-
if (!(dqrr->stat & QM_DQRR_STAT_FD_VALID))
return qman_cb_dqrr_consume;
}
mbuf->data_len = len;
}
- DPAA_PER_LCORE_RTE_CRYPTO_OP[DPAA_PER_LCORE_DPAA_SEC_OP_NB++] = ctx->op;
dpaa_sec_op_ending(ctx);
return qman_cb_dqrr_consume;