crypto/cnxk: add asymmetric capabilities
authorAnoob Joseph <anoobj@marvell.com>
Tue, 29 Jun 2021 07:34:35 +0000 (13:04 +0530)
committerAkhil Goyal <gakhil@marvell.com>
Wed, 7 Jul 2021 19:28:09 +0000 (21:28 +0200)
Add asymmetric crypto capabilities supported
by cn9k and cn10k PMDs. Documentation is also
updated for the same.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
doc/guides/cryptodevs/cnxk.rst
drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c

index db949fa..bbc6daa 100644 (file)
@@ -67,6 +67,12 @@ AEAD algorithms:
 * ``RTE_CRYPTO_AEAD_AES_GCM``
 * ``RTE_CRYPTO_AEAD_CHACHA20_POLY1305``
 
+Asymmetric Crypto Algorithms
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+* ``RTE_CRYPTO_ASYM_XFORM_RSA``
+* ``RTE_CRYPTO_ASYM_XFORM_MODEX``
+
 Installation
 ------------
 
index d52fa89..ab37f9c 100644 (file)
                                     RTE_DIM(sec_caps_##name));                \
        } while (0)
 
+static const struct rte_cryptodev_capabilities caps_mul[] = {
+       {       /* RSA */
+               .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+               {.asym = {
+                       .xform_capa = {
+                               .xform_type = RTE_CRYPTO_ASYM_XFORM_RSA,
+                               .op_types = ((1 << RTE_CRYPTO_ASYM_OP_SIGN) |
+                                       (1 << RTE_CRYPTO_ASYM_OP_VERIFY) |
+                                       (1 << RTE_CRYPTO_ASYM_OP_ENCRYPT) |
+                                       (1 << RTE_CRYPTO_ASYM_OP_DECRYPT)),
+                               {.modlen = {
+                                       .min = 17,
+                                       .max = 1024,
+                                       .increment = 1
+                               }, }
+                       }
+               }, }
+       },
+       {       /* MOD_EXP */
+               .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+               {.asym = {
+                       .xform_capa = {
+                               .xform_type = RTE_CRYPTO_ASYM_XFORM_MODEX,
+                               .op_types = 0,
+                               {.modlen = {
+                                       .min = 17,
+                                       .max = 1024,
+                                       .increment = 1
+                               }, }
+                       }
+               }, }
+       },
+       {       /* ECDSA */
+               .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+               {.asym = {
+                       .xform_capa = {
+                               .xform_type = RTE_CRYPTO_ASYM_XFORM_ECDSA,
+                               .op_types = ((1 << RTE_CRYPTO_ASYM_OP_SIGN) |
+                                       (1 << RTE_CRYPTO_ASYM_OP_VERIFY)),
+                               }
+                       },
+               }
+       },
+       {       /* ECPM */
+               .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+               {.asym = {
+                       .xform_capa = {
+                               .xform_type = RTE_CRYPTO_ASYM_XFORM_ECPM,
+                               .op_types = 0
+                               }
+                       },
+               }
+       },
+};
+
 static const struct rte_cryptodev_capabilities caps_sha1_sha2[] = {
        {       /* SHA1 */
                .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
@@ -748,6 +803,7 @@ crypto_caps_populate(struct rte_cryptodev_capabilities cnxk_caps[],
 {
        int cur_pos = 0;
 
+       CPT_CAPS_ADD(cnxk_caps, &cur_pos, hw_caps, mul);
        CPT_CAPS_ADD(cnxk_caps, &cur_pos, hw_caps, sha1_sha2);
        CPT_CAPS_ADD(cnxk_caps, &cur_pos, hw_caps, chacha20);
        CPT_CAPS_ADD(cnxk_caps, &cur_pos, hw_caps, zuc_snow3g);