common/mlx5: add register access DevX routine

The DevX routine to read/write NIC registers via DevX API is added.
This is the preparation step to check timestamp modes and units
and gather the extended statistics.

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index bb356e2..ddb14e8 100644 (file)
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -11,6 +11,67 @@
 #include "mlx5_common_utils.h"
 
 
+/**
+ * Perform read access to the registers. Reads data from register
+ * and writes ones to the specified buffer.
+ *
+ * @param[in] ctx
+ *   Context returned from mlx5 open_device() glue function.
+ * @param[in] reg_id
+ *   Register identifier according to the PRM.
+ * @param[in] arg
+ *   Register access auxiliary parameter according to the PRM.
+ * @param[out] data
+ *   Pointer to the buffer to store read data.
+ * @param[in] dw_cnt
+ *   Buffer size in double words.
+ *
+ * @return
+ *   0 on success, a negative value otherwise.
+ */
+int
+mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
+                           uint32_t *data, uint32_t dw_cnt)
+{
+       uint32_t in[MLX5_ST_SZ_DW(access_register_in)]   = {0};
+       uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
+                    MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
+       int status, rc;
+
+       MLX5_ASSERT(data && dw_cnt);
+       MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
+       if (dw_cnt  > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
+               DRV_LOG(ERR, "Not enough  buffer for register read data");
+               return -1;
+       }
+       MLX5_SET(access_register_in, in, opcode,
+                MLX5_CMD_OP_ACCESS_REGISTER_USER);
+       MLX5_SET(access_register_in, in, op_mod,
+                                       MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
+       MLX5_SET(access_register_in, in, register_id, reg_id);
+       MLX5_SET(access_register_in, in, argument, arg);
+       rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
+                                        MLX5_ST_SZ_DW(access_register_out) *
+                                        sizeof(uint32_t) + dw_cnt);
+       if (rc)
+               goto error;
+       status = MLX5_GET(access_register_out, out, status);
+       if (status) {
+               int syndrome = MLX5_GET(access_register_out, out, syndrome);
+
+               DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, "
+                              "status %x, syndrome = %x",
+                              reg_id, status, syndrome);
+               return -1;
+       }
+       memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
+              dw_cnt * sizeof(uint32_t));
+       return 0;
+error:
+       rc = (rc > 0) ? -rc : rc;
+       return rc;
+}
+
 /**
  * Allocate flow counters via devx interface.
  *

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index 7b15b5e..df83604 100644 (file)
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -385,6 +385,9 @@ __rte_internal
 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
                             struct mlx5_devx_rqt_attr *rqt_attr);
 
+__rte_internal
+int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id,
+                               uint32_t arg, uint32_t *data, uint32_t dw_cnt);
 /**
  * Create virtio queue counters object DevX API.
  *

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 2f92663..5907377 100644 (file)
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -822,6 +822,7 @@ enum {
        MLX5_CMD_OP_SUSPEND_QP = 0x50F,
        MLX5_CMD_OP_RESUME_QP = 0x510,
        MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
+       MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
        MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
        MLX5_CMD_OP_CREATE_TIR = 0x900,
        MLX5_CMD_OP_CREATE_SQ = 0X904,
@@ -841,6 +842,7 @@ enum {
        MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05,
        MLX5_CMD_SET_REGEX_REGISTERS = 0xb06,
        MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,
+       MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c,
 };
 
 enum {
@@ -2600,6 +2602,57 @@ struct mlx5_ifc_set_pp_rate_limit_context_bits {
        u8 reserved_at_60[0x120];
 };
 
+#define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u
+
+#ifdef PEDANTIC
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+struct mlx5_ifc_access_register_out_bits {
+       u8 status[0x8];
+       u8 reserved_at_8[0x18];
+       u8 syndrome[0x20];
+       u8 reserved_at_40[0x40];
+       u8 register_data[0][0x20];
+};
+
+struct mlx5_ifc_access_register_in_bits {
+       u8 opcode[0x10];
+       u8 reserved_at_10[0x10];
+       u8 reserved_at_20[0x10];
+       u8 op_mod[0x10];
+       u8 reserved_at_40[0x10];
+       u8 register_id[0x10];
+       u8 argument[0x20];
+       u8 register_data[0][0x20];
+};
+#ifdef PEDANTIC
+#pragma GCC diagnostic error "-Wpedantic"
+#endif
+
+enum {
+       MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
+       MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
+};
+
+enum {
+       MLX5_REGISTER_ID_MTUTC  = 0x9055,
+};
+
+struct mlx5_ifc_register_mtutc_bits {
+       u8 time_stamp_mode[0x2];
+       u8 time_stamp_state[0x2];
+       u8 reserved_at_4[0x18];
+       u8 operation[0x4];
+       u8 freq_adjustment[0x20];
+       u8 reserved_at_40[0x40];
+       u8 utc_sec[0x20];
+       u8 utc_nsec[0x20];
+       u8 time_adjustment[0x20];
+};
+
+#define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0
+#define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1
+
 struct regexp_params_field_select_bits {
        u8 reserved_at_0[0x1e];
        u8 stop_engine[0x1];

diff --git a/drivers/common/mlx5/rte_common_mlx5_version.map b/drivers/common/mlx5/rte_common_mlx5_version.map
index ae57ebd..68007ef 100644 (file)
--- a/drivers/common/mlx5/rte_common_mlx5_version.map
+++ b/drivers/common/mlx5/rte_common_mlx5_version.map
@@ -34,6 +34,7 @@ INTERNAL {
        mlx5_devx_cmd_query_hca_attr;
        mlx5_devx_cmd_query_virtio_q_counters;
        mlx5_devx_cmd_query_virtq;
+       mlx5_devx_cmd_register_read;
        mlx5_devx_get_out_command_status;
 
        mlx5_get_ifname_sysfs;