raw/ifpga/base: configure FEC mode

We can change the PKVL FEC mode when the A10 NIOS FW
initialization. The end-user can use this feature the
change the FEC mode, the default mode is RS FEC mode.

Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
Signed-off-by: Andy Pei <andy.pei@intel.com>

diff --git a/drivers/raw/ifpga/base/ifpga_fme.c b/drivers/raw/ifpga/base/ifpga_fme.c
index 87fa596..2bc7c10 100644 (file)
--- a/drivers/raw/ifpga/base/ifpga_fme.c
+++ b/drivers/raw/ifpga/base/ifpga_fme.c
@@ -941,9 +941,34 @@ static int nios_spi_wait_init_done(struct altera_spi_device *dev)
        u32 val = 0;
        unsigned long timeout = msecs_to_timer_cycles(10000);
        unsigned long ticks;
+       int major_version;
 
+       if (spi_reg_read(dev, NIOS_VERSION, &val))
+               return -EIO;
+
+       major_version = (val >> NIOS_VERSION_MAJOR_SHIFT) &
+               NIOS_VERSION_MAJOR;
+       dev_debug(dev, "A10 NIOS FW version %d\n", major_version);
+
+       if (major_version >= 3) {
+               /* read NIOS_INIT to check if PKVL INIT done or not */
+               if (spi_reg_read(dev, NIOS_INIT, &val))
+                       return -EIO;
+
+               /* check if PKVLs are initialized already */
+               if (val & NIOS_INIT_DONE || val & NIOS_INIT_START)
+                       goto nios_init_done;
+
+               /* start to config the default FEC mode */
+               val = NIOS_INIT_START;
+
+               if (spi_reg_write(dev, NIOS_INIT, val))
+                       return -EIO;
+       }
+
+nios_init_done:
        do {
-               if (spi_reg_read(dev, NIOS_SPI_INIT_DONE, &val))
+               if (spi_reg_read(dev, NIOS_INIT, &val))
                        return -EIO;
                if (val)
                        break;
@@ -961,23 +986,20 @@ static int nios_spi_check_error(struct altera_spi_device *dev)
 {
        u32 value = 0;
 
-       if (spi_reg_read(dev, NIOS_SPI_INIT_STS0, &value))
+       if (spi_reg_read(dev, PKVL_A_MODE_STS, &value))
                return -EIO;
 
-       dev_debug(dev, "SPI init status0 0x%x\n", value);
+       dev_debug(dev, "PKVL A Mode Status 0x%x\n", value);
 
-       /* Error code: 0xFFF0 to 0xFFFC */
-       if (value >= 0xFFF0 && value <= 0xFFFC)
+       if (value >= 0x100)
                return -EINVAL;
 
-       value = 0;
-       if (spi_reg_read(dev, NIOS_SPI_INIT_STS1, &value))
+       if (spi_reg_read(dev, PKVL_B_MODE_STS, &value))
                return -EIO;
 
-       dev_debug(dev, "SPI init status1 0x%x\n", value);
+       dev_debug(dev, "PKVL B Mode Status 0x%x\n", value);
 
-       /* Error code: 0xFFF0 to 0xFFFC */
-       if (value >= 0xFFF0 && value <= 0xFFFC)
+       if (value >= 0x100)
                return -EINVAL;
 
        return 0;

diff --git a/drivers/raw/ifpga/base/opae_spi.h b/drivers/raw/ifpga/base/opae_spi.h
index ab66e1f..6355deb 100644 (file)
--- a/drivers/raw/ifpga/base/opae_spi.h
+++ b/drivers/raw/ifpga/base/opae_spi.h
@@ -149,12 +149,19 @@ int spi_reg_read(struct altera_spi_device *dev, u32 reg, u32 *val);
 #define NIOS_SPI_STAT 0x18
 #define NIOS_SPI_VALID BIT_ULL(32)
 #define NIOS_SPI_READ_DATA GENMASK_ULL(31, 0)
-#define NIOS_SPI_INIT_DONE 0x1000
-
-#define NIOS_SPI_INIT_DONE 0x1000
-#define NIOS_SPI_INIT_STS0 0x1020
-#define NIOS_SPI_INIT_STS1 0x1024
-#define PKVL_STATUS_RESET  0
-#define PKVL_10G_MODE      1
-#define PKVL_25G_MODE      2
+
+#define NIOS_INIT              0x1000
+#define REQ_FEC_MODE           GENMASK(23, 8)
+#define FEC_MODE_NO            0x0
+#define FEC_MODE_KR            0x5555
+#define FEC_MODE_RS            0xaaaa
+#define NIOS_INIT_START                BIT(1)
+#define NIOS_INIT_DONE         BIT(0)
+#define NIOS_VERSION           0x1004
+#define NIOS_VERSION_MAJOR_SHIFT 28
+#define NIOS_VERSION_MAJOR     GENMASK(31, 28)
+#define NIOS_VERSION_MINOR     GENMASK(27, 24)
+#define NIOS_VERSION_PATCH     GENMASK(23, 20)
+#define PKVL_A_MODE_STS                0x1020
+#define PKVL_B_MODE_STS                0x1024
 #endif