#define SFC_EF100_RXQ_USER_MARK 0x20
#define SFC_EF100_RXQ_FLAG_INTR_EN 0x40
#define SFC_EF100_RXQ_INGRESS_MPORT 0x80
+#define SFC_EF100_RXQ_USER_FLAG 0x100
unsigned int ptr_mask;
unsigned int evq_phase_bit_shift;
unsigned int ready_pkts;
EFX_RX_PREFIX_FIELD(INGRESS_MPORT,
ESF_GZ_RX_PREFIX_INGRESS_MPORT, B_FALSE),
SFC_EF100_RX_PREFIX_FIELD(RSS_HASH, B_FALSE),
+ SFC_EF100_RX_PREFIX_FIELD(USER_FLAG, B_FALSE),
SFC_EF100_RX_PREFIX_FIELD(USER_MARK, B_FALSE),
#undef SFC_EF100_RX_PREFIX_FIELD
ESF_GZ_RX_PREFIX_RSS_HASH);
}
+ if (rxq->flags & SFC_EF100_RXQ_USER_FLAG) {
+ uint32_t user_flag;
+
+ user_flag = EFX_XWORD_FIELD(rx_prefix[0],
+ ESF_GZ_RX_PREFIX_USER_FLAG);
+ if (user_flag != 0)
+ ol_flags |= PKT_RX_FDIR;
+ }
+
if (rxq->flags & SFC_EF100_RXQ_USER_MARK) {
uint32_t user_mark;
else
rxq->flags &= ~SFC_EF100_RXQ_RSS_HASH;
+ if ((unsup_rx_prefix_fields &
+ (1U << EFX_RX_PREFIX_FIELD_USER_FLAG)) == 0)
+ rxq->flags |= SFC_EF100_RXQ_USER_FLAG;
+ else
+ rxq->flags &= ~SFC_EF100_RXQ_USER_FLAG;
+
if ((unsup_rx_prefix_fields &
(1U << EFX_RX_PREFIX_FIELD_USER_MARK)) == 0)
rxq->flags |= SFC_EF100_RXQ_USER_MARK;
.hw_fw_caps = SFC_DP_HW_FW_CAP_EF100,
},
.features = SFC_DP_RX_FEAT_MULTI_PROCESS |
+ SFC_DP_RX_FEAT_FLOW_FLAG |
SFC_DP_RX_FEAT_FLOW_MARK |
SFC_DP_RX_FEAT_INTR |
SFC_DP_RX_FEAT_STATS,
if (offloads & DEV_RX_OFFLOAD_RSS_HASH)
rxq_info->type_flags |= EFX_RXQ_FLAG_RSS_HASH;
+ if ((sa->negotiated_rx_metadata & RTE_ETH_RX_METADATA_USER_FLAG) != 0)
+ rxq_info->type_flags |= EFX_RXQ_FLAG_USER_FLAG;
+
if ((sa->negotiated_rx_metadata & RTE_ETH_RX_METADATA_USER_MARK) != 0)
rxq_info->type_flags |= EFX_RXQ_FLAG_USER_MARK;