#define __ECORE_H
#include "ecore_hsi_common.h"
-#include "ecore_hsi_tools.h"
+#include "ecore_hsi_debug_tools.h"
+#include "ecore_hsi_init_func.h"
+#include "ecore_hsi_init_tool.h"
#include "ecore_proto_if.h"
#include "mcp_public.h"
#define ECORE_DEV_TYPE_AH (1 << 0)
/* Translate type/revision combo into the proper conditions */
#define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB)
-#define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && \
- CHIP_REV_IS_A0(dev))
-#define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && \
- CHIP_REV_IS_B0(dev))
+#define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
+#ifndef ASIC_ONLY
+#define ECORE_IS_BB_B0(dev) ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
+ (CHIP_REV_IS_TEDIBEAR(dev)))
+#else
+#define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
+#endif
#define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH)
#define ECORE_IS_K2(dev) ECORE_IS_AH(dev)
-#define ECORE_GET_TYPE(dev) (ECORE_IS_BB_A0(dev) ? CHIP_BB_A0 : \
- ECORE_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)
u16 vendor_id;
u16 device_id;
for (i = 0; i < num_ports; i++) {
p_qm_port = &qm_info->qm_port_params[i];
p_qm_port->active = 1;
- /* @@@TMP - was NUM_OF_PHYS_TCS; Changed until dcbx will
- * be in place
- */
- if (num_ports == 4)
- p_qm_port->num_active_phys_tcs = 2;
- else
- p_qm_port->num_active_phys_tcs = 5;
p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
}
{
int hw_mode = 0;
- switch (ECORE_GET_TYPE(p_hwfn->p_dev)) {
- case CHIP_BB_A0:
+ if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
hw_mode |= 1 << MODE_BB_A0;
- break;
- case CHIP_BB_B0:
+ } else if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
hw_mode |= 1 << MODE_BB_B0;
- break;
- case CHIP_K2:
+ } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
hw_mode |= 1 << MODE_K2;
- break;
- default:
- DP_NOTICE(p_hwfn, true, "Can't initialize chip ID %d\n",
- ECORE_GET_TYPE(p_hwfn->p_dev));
+ } else {
+ DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
+ p_hwfn->p_dev->type);
return;
}
if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2, 0x3ffffff);
- /* initialize interrupt masks */
- for (i = 0;
- i <
- attn_blocks[BLOCK_MISCS].chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].
- num_of_int_regs; i++)
- ecore_wr(p_hwfn, p_ptt,
- attn_blocks[BLOCK_MISCS].
- chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[i]->
- mask_addr, 0);
-
- if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev))
- ecore_wr(p_hwfn, p_ptt,
- attn_blocks[BLOCK_CNIG].
- chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[0]->
- mask_addr, 0);
- ecore_wr(p_hwfn, p_ptt,
- attn_blocks[BLOCK_PGLCS].
- chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[0]->
- mask_addr, 0);
- ecore_wr(p_hwfn, p_ptt,
- attn_blocks[BLOCK_CPMU].
- chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[0]->
- mask_addr, 0);
- /* Currently A0 and B0 interrupt bits are the same in pglue_b;
- * If this changes, need to set this according to chip type. <14/09/23>
- */
- ecore_wr(p_hwfn, p_ptt,
- attn_blocks[BLOCK_PGLUE_B].
- chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[0]->
- mask_addr, 0x80000);
-
/* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
/* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev))
* &ctrl);
*/
-#ifndef ASIC_ONLY
- /*@@TMP - On B0 build 1, need to mask the datapath_registers parity */
- if (CHIP_REV_IS_EMUL_B0(p_hwfn->p_dev) &&
- (p_hwfn->p_dev->chip_metal == 1)) {
- u32 reg_addr, tmp;
-
- reg_addr =
- attn_blocks[BLOCK_PGLUE_B].
- chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].prty_regs[0]->
- mask_addr;
- DP_NOTICE(p_hwfn, false,
- "Masking datapath registers parity on"
- " B0 emulation [build 1]\n");
- tmp = ecore_rd(p_hwfn, p_ptt, reg_addr);
- tmp |= (1 << 0); /* Was PRTY_MASK_DATAPATH_REGISTERS */
- ecore_wr(p_hwfn, p_ptt, reg_addr, tmp);
- }
-#endif
-
rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
if (rc)
return rc;
__le32 reserved1;
};
-enum block_addr {
- GRCBASE_GRC = 0x50000,
- GRCBASE_MISCS = 0x9000,
- GRCBASE_MISC = 0x8000,
- GRCBASE_DBU = 0xa000,
- GRCBASE_PGLUE_B = 0x2a8000,
- GRCBASE_CNIG = 0x218000,
- GRCBASE_CPMU = 0x30000,
- GRCBASE_NCSI = 0x40000,
- GRCBASE_OPTE = 0x53000,
- GRCBASE_BMB = 0x540000,
- GRCBASE_PCIE = 0x54000,
- GRCBASE_MCP = 0xe00000,
- GRCBASE_MCP2 = 0x52000,
- GRCBASE_PSWHST = 0x2a0000,
- GRCBASE_PSWHST2 = 0x29e000,
- GRCBASE_PSWRD = 0x29c000,
- GRCBASE_PSWRD2 = 0x29d000,
- GRCBASE_PSWWR = 0x29a000,
- GRCBASE_PSWWR2 = 0x29b000,
- GRCBASE_PSWRQ = 0x280000,
- GRCBASE_PSWRQ2 = 0x240000,
- GRCBASE_PGLCS = 0x0,
- GRCBASE_DMAE = 0xc000,
- GRCBASE_PTU = 0x560000,
- GRCBASE_TCM = 0x1180000,
- GRCBASE_MCM = 0x1200000,
- GRCBASE_UCM = 0x1280000,
- GRCBASE_XCM = 0x1000000,
- GRCBASE_YCM = 0x1080000,
- GRCBASE_PCM = 0x1100000,
- GRCBASE_QM = 0x2f0000,
- GRCBASE_TM = 0x2c0000,
- GRCBASE_DORQ = 0x100000,
- GRCBASE_BRB = 0x340000,
- GRCBASE_SRC = 0x238000,
- GRCBASE_PRS = 0x1f0000,
- GRCBASE_TSDM = 0xfb0000,
- GRCBASE_MSDM = 0xfc0000,
- GRCBASE_USDM = 0xfd0000,
- GRCBASE_XSDM = 0xf80000,
- GRCBASE_YSDM = 0xf90000,
- GRCBASE_PSDM = 0xfa0000,
- GRCBASE_TSEM = 0x1700000,
- GRCBASE_MSEM = 0x1800000,
- GRCBASE_USEM = 0x1900000,
- GRCBASE_XSEM = 0x1400000,
- GRCBASE_YSEM = 0x1500000,
- GRCBASE_PSEM = 0x1600000,
- GRCBASE_RSS = 0x238800,
- GRCBASE_TMLD = 0x4d0000,
- GRCBASE_MULD = 0x4e0000,
- GRCBASE_YULD = 0x4c8000,
- GRCBASE_XYLD = 0x4c0000,
- GRCBASE_PRM = 0x230000,
- GRCBASE_PBF_PB1 = 0xda0000,
- GRCBASE_PBF_PB2 = 0xda4000,
- GRCBASE_RPB = 0x23c000,
- GRCBASE_BTB = 0xdb0000,
- GRCBASE_PBF = 0xd80000,
- GRCBASE_RDIF = 0x300000,
- GRCBASE_TDIF = 0x310000,
- GRCBASE_CDU = 0x580000,
- GRCBASE_CCFC = 0x2e0000,
- GRCBASE_TCFC = 0x2d0000,
- GRCBASE_IGU = 0x180000,
- GRCBASE_CAU = 0x1c0000,
- GRCBASE_UMAC = 0x51000,
- GRCBASE_XMAC = 0x210000,
- GRCBASE_DBG = 0x10000,
- GRCBASE_NIG = 0x500000,
- GRCBASE_WOL = 0x600000,
- GRCBASE_BMBN = 0x610000,
- GRCBASE_IPC = 0x20000,
- GRCBASE_NWM = 0x800000,
- GRCBASE_NWS = 0x700000,
- GRCBASE_MS = 0x6a0000,
- GRCBASE_PHY_PCIE = 0x620000,
- GRCBASE_MISC_AEU = 0x8000,
- GRCBASE_BAR0_MAP = 0x1c00000,
- MAX_BLOCK_ADDR
-};
-
-enum block_id {
- BLOCK_GRC,
- BLOCK_MISCS,
- BLOCK_MISC,
- BLOCK_DBU,
- BLOCK_PGLUE_B,
- BLOCK_CNIG,
- BLOCK_CPMU,
- BLOCK_NCSI,
- BLOCK_OPTE,
- BLOCK_BMB,
- BLOCK_PCIE,
- BLOCK_MCP,
- BLOCK_MCP2,
- BLOCK_PSWHST,
- BLOCK_PSWHST2,
- BLOCK_PSWRD,
- BLOCK_PSWRD2,
- BLOCK_PSWWR,
- BLOCK_PSWWR2,
- BLOCK_PSWRQ,
- BLOCK_PSWRQ2,
- BLOCK_PGLCS,
- BLOCK_DMAE,
- BLOCK_PTU,
- BLOCK_TCM,
- BLOCK_MCM,
- BLOCK_UCM,
- BLOCK_XCM,
- BLOCK_YCM,
- BLOCK_PCM,
- BLOCK_QM,
- BLOCK_TM,
- BLOCK_DORQ,
- BLOCK_BRB,
- BLOCK_SRC,
- BLOCK_PRS,
- BLOCK_TSDM,
- BLOCK_MSDM,
- BLOCK_USDM,
- BLOCK_XSDM,
- BLOCK_YSDM,
- BLOCK_PSDM,
- BLOCK_TSEM,
- BLOCK_MSEM,
- BLOCK_USEM,
- BLOCK_XSEM,
- BLOCK_YSEM,
- BLOCK_PSEM,
- BLOCK_RSS,
- BLOCK_TMLD,
- BLOCK_MULD,
- BLOCK_YULD,
- BLOCK_XYLD,
- BLOCK_PRM,
- BLOCK_PBF_PB1,
- BLOCK_PBF_PB2,
- BLOCK_RPB,
- BLOCK_BTB,
- BLOCK_PBF,
- BLOCK_RDIF,
- BLOCK_TDIF,
- BLOCK_CDU,
- BLOCK_CCFC,
- BLOCK_TCFC,
- BLOCK_IGU,
- BLOCK_CAU,
- BLOCK_UMAC,
- BLOCK_XMAC,
- BLOCK_DBG,
- BLOCK_NIG,
- BLOCK_WOL,
- BLOCK_BMBN,
- BLOCK_IPC,
- BLOCK_NWM,
- BLOCK_NWS,
- BLOCK_MS,
- BLOCK_PHY_PCIE,
- BLOCK_MISC_AEU,
- BLOCK_BAR0_MAP,
- MAX_BLOCK_ID
-};
-
/*
* Igu cleanup bit values to distinguish between clean or producer consumer
*/
__le16 xsum8 /* checksum8 result */;
};
-struct fw_ver_num {
- u8 major /* Firmware major version number */;
- u8 minor /* Firmware minor version number */;
- u8 rev /* Firmware revision version number */;
- u8 eng /* Firmware engineering version number (for bootleg versions) */
- ;
-};
-
-struct fw_ver_info {
- __le16 tools_ver /* Tools version number */;
- u8 image_id /* FW image ID (e.g. main, l2b, kuku) */;
- u8 reserved1;
- struct fw_ver_num num /* FW version number */;
- __le32 timestamp /* FW Timestamp in unix time (sec. since 1970) */;
- __le32 reserved2;
-};
-
struct storm_ram_section {
__le16 offset
/* The offset of the section in the RAM (in 64 bit units) */;
__le16 size /* The size of the section (in 64 bit units) */;
};
-struct fw_info {
- struct fw_ver_info ver /* FW version information */;
- struct storm_ram_section fw_asserts_section
- /* The FW Asserts offset/size in Storm RAM */;
- __le32 reserved;
-};
-
-struct fw_info_location {
- __le32 grc_addr /* GRC address where the fw_info struct is located. */;
- __le32 size
- /* Size of the fw_info structure (thats located at the grc_addr). */
- ;
-};
-
/*
* IGU cleanup command
*/
#define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24
};
-enum init_modes {
- MODE_BB_A0,
- MODE_BB_B0,
- MODE_K2,
- MODE_ASIC,
- MODE_EMUL_REDUCED,
- MODE_EMUL_FULL,
- MODE_FPGA,
- MODE_CHIPSIM,
- MODE_SF,
- MODE_MF_SD,
- MODE_MF_SI,
- MODE_PORTS_PER_ENG_1,
- MODE_PORTS_PER_ENG_2,
- MODE_PORTS_PER_ENG_4,
- MODE_100G,
- MODE_EAGLE_ENG1_WORKAROUND,
- MAX_INIT_MODES
-};
-
-enum init_phases {
- PHASE_ENGINE,
- PHASE_PORT,
- PHASE_PF,
- PHASE_VF,
- PHASE_QM_PF,
- MAX_INIT_PHASES
-};
-
struct mstorm_core_conn_ag_ctx {
u8 byte0 /* cdu_validation */;
u8 byte1 /* state */;
--- /dev/null
+/*
+ * Copyright (c) 2016 QLogic Corporation.
+ * All rights reserved.
+ * www.qlogic.com
+ *
+ * See LICENSE.qede_pmd for copyright and licensing details.
+ */
+
+#ifndef __ECORE_HSI_DEBUG_TOOLS__
+#define __ECORE_HSI_DEBUG_TOOLS__
+/****************************************/
+/* Debug Tools HSI constants and macros */
+/****************************************/
+
+
+enum block_addr {
+ GRCBASE_GRC = 0x50000,
+ GRCBASE_MISCS = 0x9000,
+ GRCBASE_MISC = 0x8000,
+ GRCBASE_DBU = 0xa000,
+ GRCBASE_PGLUE_B = 0x2a8000,
+ GRCBASE_CNIG = 0x218000,
+ GRCBASE_CPMU = 0x30000,
+ GRCBASE_NCSI = 0x40000,
+ GRCBASE_OPTE = 0x53000,
+ GRCBASE_BMB = 0x540000,
+ GRCBASE_PCIE = 0x54000,
+ GRCBASE_MCP = 0xe00000,
+ GRCBASE_MCP2 = 0x52000,
+ GRCBASE_PSWHST = 0x2a0000,
+ GRCBASE_PSWHST2 = 0x29e000,
+ GRCBASE_PSWRD = 0x29c000,
+ GRCBASE_PSWRD2 = 0x29d000,
+ GRCBASE_PSWWR = 0x29a000,
+ GRCBASE_PSWWR2 = 0x29b000,
+ GRCBASE_PSWRQ = 0x280000,
+ GRCBASE_PSWRQ2 = 0x240000,
+ GRCBASE_PGLCS = 0x0,
+ GRCBASE_DMAE = 0xc000,
+ GRCBASE_PTU = 0x560000,
+ GRCBASE_TCM = 0x1180000,
+ GRCBASE_MCM = 0x1200000,
+ GRCBASE_UCM = 0x1280000,
+ GRCBASE_XCM = 0x1000000,
+ GRCBASE_YCM = 0x1080000,
+ GRCBASE_PCM = 0x1100000,
+ GRCBASE_QM = 0x2f0000,
+ GRCBASE_TM = 0x2c0000,
+ GRCBASE_DORQ = 0x100000,
+ GRCBASE_BRB = 0x340000,
+ GRCBASE_SRC = 0x238000,
+ GRCBASE_PRS = 0x1f0000,
+ GRCBASE_TSDM = 0xfb0000,
+ GRCBASE_MSDM = 0xfc0000,
+ GRCBASE_USDM = 0xfd0000,
+ GRCBASE_XSDM = 0xf80000,
+ GRCBASE_YSDM = 0xf90000,
+ GRCBASE_PSDM = 0xfa0000,
+ GRCBASE_TSEM = 0x1700000,
+ GRCBASE_MSEM = 0x1800000,
+ GRCBASE_USEM = 0x1900000,
+ GRCBASE_XSEM = 0x1400000,
+ GRCBASE_YSEM = 0x1500000,
+ GRCBASE_PSEM = 0x1600000,
+ GRCBASE_RSS = 0x238800,
+ GRCBASE_TMLD = 0x4d0000,
+ GRCBASE_MULD = 0x4e0000,
+ GRCBASE_YULD = 0x4c8000,
+ GRCBASE_XYLD = 0x4c0000,
+ GRCBASE_PRM = 0x230000,
+ GRCBASE_PBF_PB1 = 0xda0000,
+ GRCBASE_PBF_PB2 = 0xda4000,
+ GRCBASE_RPB = 0x23c000,
+ GRCBASE_BTB = 0xdb0000,
+ GRCBASE_PBF = 0xd80000,
+ GRCBASE_RDIF = 0x300000,
+ GRCBASE_TDIF = 0x310000,
+ GRCBASE_CDU = 0x580000,
+ GRCBASE_CCFC = 0x2e0000,
+ GRCBASE_TCFC = 0x2d0000,
+ GRCBASE_IGU = 0x180000,
+ GRCBASE_CAU = 0x1c0000,
+ GRCBASE_UMAC = 0x51000,
+ GRCBASE_XMAC = 0x210000,
+ GRCBASE_DBG = 0x10000,
+ GRCBASE_NIG = 0x500000,
+ GRCBASE_WOL = 0x600000,
+ GRCBASE_BMBN = 0x610000,
+ GRCBASE_IPC = 0x20000,
+ GRCBASE_NWM = 0x800000,
+ GRCBASE_NWS = 0x700000,
+ GRCBASE_MS = 0x6a0000,
+ GRCBASE_PHY_PCIE = 0x620000,
+ GRCBASE_LED = 0x6b8000,
+ GRCBASE_MISC_AEU = 0x8000,
+ GRCBASE_BAR0_MAP = 0x1c00000,
+ MAX_BLOCK_ADDR
+};
+
+
+enum block_id {
+ BLOCK_GRC,
+ BLOCK_MISCS,
+ BLOCK_MISC,
+ BLOCK_DBU,
+ BLOCK_PGLUE_B,
+ BLOCK_CNIG,
+ BLOCK_CPMU,
+ BLOCK_NCSI,
+ BLOCK_OPTE,
+ BLOCK_BMB,
+ BLOCK_PCIE,
+ BLOCK_MCP,
+ BLOCK_MCP2,
+ BLOCK_PSWHST,
+ BLOCK_PSWHST2,
+ BLOCK_PSWRD,
+ BLOCK_PSWRD2,
+ BLOCK_PSWWR,
+ BLOCK_PSWWR2,
+ BLOCK_PSWRQ,
+ BLOCK_PSWRQ2,
+ BLOCK_PGLCS,
+ BLOCK_DMAE,
+ BLOCK_PTU,
+ BLOCK_TCM,
+ BLOCK_MCM,
+ BLOCK_UCM,
+ BLOCK_XCM,
+ BLOCK_YCM,
+ BLOCK_PCM,
+ BLOCK_QM,
+ BLOCK_TM,
+ BLOCK_DORQ,
+ BLOCK_BRB,
+ BLOCK_SRC,
+ BLOCK_PRS,
+ BLOCK_TSDM,
+ BLOCK_MSDM,
+ BLOCK_USDM,
+ BLOCK_XSDM,
+ BLOCK_YSDM,
+ BLOCK_PSDM,
+ BLOCK_TSEM,
+ BLOCK_MSEM,
+ BLOCK_USEM,
+ BLOCK_XSEM,
+ BLOCK_YSEM,
+ BLOCK_PSEM,
+ BLOCK_RSS,
+ BLOCK_TMLD,
+ BLOCK_MULD,
+ BLOCK_YULD,
+ BLOCK_XYLD,
+ BLOCK_PRM,
+ BLOCK_PBF_PB1,
+ BLOCK_PBF_PB2,
+ BLOCK_RPB,
+ BLOCK_BTB,
+ BLOCK_PBF,
+ BLOCK_RDIF,
+ BLOCK_TDIF,
+ BLOCK_CDU,
+ BLOCK_CCFC,
+ BLOCK_TCFC,
+ BLOCK_IGU,
+ BLOCK_CAU,
+ BLOCK_UMAC,
+ BLOCK_XMAC,
+ BLOCK_DBG,
+ BLOCK_NIG,
+ BLOCK_WOL,
+ BLOCK_BMBN,
+ BLOCK_IPC,
+ BLOCK_NWM,
+ BLOCK_NWS,
+ BLOCK_MS,
+ BLOCK_PHY_PCIE,
+ BLOCK_LED,
+ BLOCK_MISC_AEU,
+ BLOCK_BAR0_MAP,
+ MAX_BLOCK_ID
+};
+
+
+/*
+ * binary debug buffer types
+ */
+enum bin_dbg_buffer_type {
+ BIN_BUF_DBG_MODE_TREE /* init modes tree */,
+ BIN_BUF_DBG_DUMP_REG /* GRC Dump registers */,
+ BIN_BUF_DBG_DUMP_MEM /* GRC Dump memories */,
+ BIN_BUF_DBG_IDLE_CHK_REGS /* Idle Check registers */,
+ BIN_BUF_DBG_IDLE_CHK_IMMS /* Idle Check immediates */,
+ BIN_BUF_DBG_IDLE_CHK_RULES /* Idle Check rules */,
+ BIN_BUF_DBG_IDLE_CHK_PARSING_DATA /* Idle Check parsing data */,
+ BIN_BUF_DBG_ATTN_BLOCKS /* Attention blocks */,
+ BIN_BUF_DBG_ATTN_REGS /* Attention registers */,
+ BIN_BUF_DBG_ATTN_INDEXES /* Attention indexes */,
+ BIN_BUF_DBG_ATTN_NAME_OFFSETS /* Attention name offsets */,
+ BIN_BUF_DBG_PARSING_STRINGS /* Debug Tools parsing strings */,
+ MAX_BIN_DBG_BUFFER_TYPE
+};
+
+
+/*
+ * Attention bit mapping
+ */
+struct dbg_attn_bit_mapping {
+ __le16 data;
+/* The index of an attention in the blocks attentions list
+ * (if is_unused_idx_cnt=0), or a number of consecutive unused attention bits
+ * (if is_unused_idx_cnt=1)
+ */
+#define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF
+#define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0
+/* if set, the val field indicates the number of consecutive unused attention
+ * bits
+ */
+#define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1
+#define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15
+};
+
+
+/*
+ * Attention block per-type data
+ */
+struct dbg_attn_block_type_data {
+/* Offset of this block attention names in the debug attention name offsets
+ * array
+ */
+ __le16 names_offset;
+ __le16 reserved1;
+ u8 num_regs /* Number of attention registers in this block */;
+ u8 reserved2;
+/* Offset of this blocks attention registers in the attention registers array
+ * (in dbg_attn_reg units)
+ */
+ __le16 regs_offset;
+};
+
+/*
+ * Block attentions
+ */
+struct dbg_attn_block {
+/* attention block per-type data. Count must match the number of elements in
+ * dbg_attn_type.
+ */
+ struct dbg_attn_block_type_data per_type_data[2];
+};
+
+
+/*
+ * Attention register result
+ */
+struct dbg_attn_reg_result {
+ __le32 data;
+/* STS attention register GRC address (in dwords) */
+#define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF
+#define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0
+/* Number of attention indexes in this register */
+#define DBG_ATTN_REG_RESULT_NUM_ATTN_IDX_MASK 0xFF
+#define DBG_ATTN_REG_RESULT_NUM_ATTN_IDX_SHIFT 24
+/* Offset of this registers block attention indexes (values in the range
+ * 0..number of block attentions)
+ */
+ __le16 attn_idx_offset;
+ __le16 reserved;
+ __le32 sts_val /* Value read from the STS attention register */;
+ __le32 mask_val /* Value read from the MASK attention register */;
+};
+
+/*
+ * Attention block result
+ */
+struct dbg_attn_block_result {
+ u8 block_id /* Registers block ID */;
+ u8 data;
+/* Value from dbg_attn_type enum */
+#define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3
+#define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0
+/* Number of registers in the blok in which at least one attention bit is set */
+#define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F
+#define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2
+/* Offset of this registers block attention names in the attention name offsets
+ * array
+ */
+ __le16 names_offset;
+/* result data for each register in the block in which at least one attention
+ * bit is set
+ */
+ struct dbg_attn_reg_result reg_results[15];
+};
+
+
+
+/*
+ * mode header
+ */
+struct dbg_mode_hdr {
+ __le16 data;
+/* indicates if a mode expression should be evaluated (0/1) */
+#define DBG_MODE_HDR_EVAL_MODE_MASK 0x1
+#define DBG_MODE_HDR_EVAL_MODE_SHIFT 0
+/* offset (in bytes) in modes expression buffer. valid only if eval_mode is
+ * set.
+ */
+#define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF
+#define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1
+};
+
+/*
+ * Attention register
+ */
+struct dbg_attn_reg {
+ struct dbg_mode_hdr mode /* Mode header */;
+/* Offset of this registers block attention indexes (values in the range
+ * 0..number of block attentions)
+ */
+ __le16 attn_idx_offset;
+ __le32 data;
+/* STS attention register GRC address (in dwords) */
+#define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF
+#define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0
+/* Number of attention indexes in this register */
+#define DBG_ATTN_REG_NUM_ATTN_IDX_MASK 0xFF
+#define DBG_ATTN_REG_NUM_ATTN_IDX_SHIFT 24
+/* STS_CLR attention register GRC address (in dwords) */
+ __le32 sts_clr_address;
+/* MASK attention register GRC address (in dwords) */
+ __le32 mask_address;
+};
+
+
+
+/*
+ * attention types
+ */
+enum dbg_attn_type {
+ ATTN_TYPE_INTERRUPT,
+ ATTN_TYPE_PARITY,
+ MAX_DBG_ATTN_TYPE
+};
+
+
+/*
+ * condition header for registers dump
+ */
+struct dbg_dump_cond_hdr {
+ struct dbg_mode_hdr mode /* Mode header */;
+ u8 block_id /* block ID */;
+ u8 data_size /* size in dwords of the data following this header */;
+};
+
+
+/*
+ * memory data for registers dump
+ */
+struct dbg_dump_mem {
+ __le32 dword0;
+/* register address (in dwords) */
+#define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF
+#define DBG_DUMP_MEM_ADDRESS_SHIFT 0
+#define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF /* memory group ID */
+#define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24
+ __le32 dword1;
+/* register size (in dwords) */
+#define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF
+#define DBG_DUMP_MEM_LENGTH_SHIFT 0
+#define DBG_DUMP_MEM_RESERVED_MASK 0xFF
+#define DBG_DUMP_MEM_RESERVED_SHIFT 24
+};
+
+
+/*
+ * register data for registers dump
+ */
+struct dbg_dump_reg {
+ __le32 data;
+/* register address (in dwords) */
+#define DBG_DUMP_REG_ADDRESS_MASK 0xFFFFFF
+#define DBG_DUMP_REG_ADDRESS_SHIFT 0
+#define DBG_DUMP_REG_LENGTH_MASK 0xFF /* register size (in dwords) */
+#define DBG_DUMP_REG_LENGTH_SHIFT 24
+};
+
+
+/*
+ * split header for registers dump
+ */
+struct dbg_dump_split_hdr {
+ __le32 hdr;
+/* size in dwords of the data following this header */
+#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF
+#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0
+#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF /* split type ID */
+#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24
+};
+
+
+/*
+ * condition header for idle check
+ */
+struct dbg_idle_chk_cond_hdr {
+ struct dbg_mode_hdr mode /* Mode header */;
+/* size in dwords of the data following this header */
+ __le16 data_size;
+};
+
+
+/*
+ * Idle Check condition register
+ */
+struct dbg_idle_chk_cond_reg {
+ __le32 data;
+/* Register GRC address (in dwords) */
+#define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0xFFFFFF
+#define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0
+/* value from block_id enum */
+#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF
+#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24
+ __le16 num_entries /* number of registers entries to check */;
+ u8 entry_size /* size of registers entry (in dwords) */;
+ u8 start_entry /* index of the first entry to check */;
+};
+
+
+/*
+ * Idle Check info register
+ */
+struct dbg_idle_chk_info_reg {
+ __le32 data;
+/* Register GRC address (in dwords) */
+#define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0xFFFFFF
+#define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0
+/* value from block_id enum */
+#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF
+#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24
+ __le16 size /* register size in dwords */;
+ struct dbg_mode_hdr mode /* Mode header */;
+};
+
+
+/*
+ * Idle Check register
+ */
+union dbg_idle_chk_reg {
+ struct dbg_idle_chk_cond_reg cond_reg /* condition register */;
+ struct dbg_idle_chk_info_reg info_reg /* info register */;
+};
+
+
+/*
+ * Idle Check result header
+ */
+struct dbg_idle_chk_result_hdr {
+ __le16 rule_id /* Failing rule index */;
+ __le16 mem_entry_id /* Failing memory entry index */;
+ u8 num_dumped_cond_regs /* number of dumped condition registers */;
+ u8 num_dumped_info_regs /* number of dumped condition registers */;
+ u8 severity /* from dbg_idle_chk_severity_types enum */;
+ u8 reserved;
+};
+
+
+/*
+ * Idle Check result register header
+ */
+struct dbg_idle_chk_result_reg_hdr {
+ u8 data;
+/* indicates if this register is a memory */
+#define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1
+#define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0
+/* register index within the failing rule */
+#define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F
+#define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1
+ u8 start_entry /* index of the first checked entry */;
+ __le16 size /* register size in dwords */;
+};
+
+
+/*
+ * Idle Check rule
+ */
+struct dbg_idle_chk_rule {
+ __le16 rule_id /* Idle Check rule ID */;
+ u8 severity /* value from dbg_idle_chk_severity_types enum */;
+ u8 cond_id /* Condition ID */;
+ u8 num_cond_regs /* number of condition registers */;
+ u8 num_info_regs /* number of info registers */;
+ u8 num_imms /* number of immediates in the condition */;
+ u8 reserved1;
+/* offset of this rules registers in the idle check register array
+ * (in dbg_idle_chk_reg units)
+ */
+ __le16 reg_offset;
+/* offset of this rules immediate values in the immediate values array
+ * (in dwords)
+ */
+ __le16 imm_offset;
+};
+
+
+/*
+ * Idle Check rule parsing data
+ */
+struct dbg_idle_chk_rule_parsing_data {
+ __le32 data;
+/* indicates if this register has a FW message */
+#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1
+#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0
+/* Offset of this rules strings in the debug strings array (in bytes) */
+#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF
+#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1
+};
+
+
+/*
+ * idle check severity types
+ */
+enum dbg_idle_chk_severity_types {
+/* idle check failure should cause an error */
+ IDLE_CHK_SEVERITY_ERROR,
+/* idle check failure should cause an error only if theres no traffic */
+ IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC,
+/* idle check failure should cause a warning */
+ IDLE_CHK_SEVERITY_WARNING,
+ MAX_DBG_IDLE_CHK_SEVERITY_TYPES
+};
+
+
+
+/*
+ * Debug Bus block data
+ */
+struct dbg_bus_block_data {
+/* Indicates if the block is enabled for recording (0/1) */
+ u8 enabled;
+ u8 hw_id /* HW ID associated with the block */;
+ u8 line_num /* Debug line number to select */;
+ u8 right_shift /* Number of units to right the debug data (0-3) */;
+ u8 cycle_en /* 4-bit value: bit i set -> unit i is enabled. */;
+/* 4-bit value: bit i set -> unit i is forced valid. */
+ u8 force_valid;
+/* 4-bit value: bit i set -> unit i frame bit is forced. */
+ u8 force_frame;
+ u8 reserved;
+};
+
+
+/*
+ * Debug Bus Clients
+ */
+enum dbg_bus_clients {
+ DBG_BUS_CLIENT_RBCN,
+ DBG_BUS_CLIENT_RBCP,
+ DBG_BUS_CLIENT_RBCR,
+ DBG_BUS_CLIENT_RBCT,
+ DBG_BUS_CLIENT_RBCU,
+ DBG_BUS_CLIENT_RBCF,
+ DBG_BUS_CLIENT_RBCX,
+ DBG_BUS_CLIENT_RBCS,
+ DBG_BUS_CLIENT_RBCH,
+ DBG_BUS_CLIENT_RBCZ,
+ DBG_BUS_CLIENT_OTHER_ENGINE,
+ DBG_BUS_CLIENT_TIMESTAMP,
+ DBG_BUS_CLIENT_CPU,
+ DBG_BUS_CLIENT_RBCY,
+ DBG_BUS_CLIENT_RBCQ,
+ DBG_BUS_CLIENT_RBCM,
+ DBG_BUS_CLIENT_RBCB,
+ DBG_BUS_CLIENT_RBCW,
+ DBG_BUS_CLIENT_RBCV,
+ MAX_DBG_BUS_CLIENTS
+};
+
+
+/*
+ * Debug Bus constraint operation types
+ */
+enum dbg_bus_constraint_ops {
+ DBG_BUS_CONSTRAINT_OP_EQ /* equal */,
+ DBG_BUS_CONSTRAINT_OP_NE /* not equal */,
+ DBG_BUS_CONSTRAINT_OP_LT /* less than */,
+ DBG_BUS_CONSTRAINT_OP_LTC /* less than (cyclic) */,
+ DBG_BUS_CONSTRAINT_OP_LE /* less than or equal */,
+ DBG_BUS_CONSTRAINT_OP_LEC /* less than or equal (cyclic) */,
+ DBG_BUS_CONSTRAINT_OP_GT /* greater than */,
+ DBG_BUS_CONSTRAINT_OP_GTC /* greater than (cyclic) */,
+ DBG_BUS_CONSTRAINT_OP_GE /* greater than or equal */,
+ DBG_BUS_CONSTRAINT_OP_GEC /* greater than or equal (cyclic) */,
+ MAX_DBG_BUS_CONSTRAINT_OPS
+};
+
+
+/*
+ * Debug Bus memory address
+ */
+struct dbg_bus_mem_addr {
+ __le32 lo;
+ __le32 hi;
+};
+
+/*
+ * Debug Bus PCI buffer data
+ */
+struct dbg_bus_pci_buf_data {
+ struct dbg_bus_mem_addr phys_addr /* PCI buffer physical address */;
+ struct dbg_bus_mem_addr virt_addr /* PCI buffer virtual address */;
+ __le32 size /* PCI buffer size in bytes */;
+};
+
+/*
+ * Debug Bus Storm EID range filter params
+ */
+struct dbg_bus_storm_eid_range_params {
+ u8 min /* Minimal event ID to filter on */;
+ u8 max /* Maximal event ID to filter on */;
+};
+
+/*
+ * Debug Bus Storm EID mask filter params
+ */
+struct dbg_bus_storm_eid_mask_params {
+ u8 val /* Event ID value */;
+ u8 mask /* Event ID mask. 1s in the mask = dont care bits. */;
+};
+
+/*
+ * Debug Bus Storm EID filter params
+ */
+union dbg_bus_storm_eid_params {
+/* EID range filter params */
+ struct dbg_bus_storm_eid_range_params range;
+/* EID mask filter params */
+ struct dbg_bus_storm_eid_mask_params mask;
+};
+
+/*
+ * Debug Bus Storm data
+ */
+struct dbg_bus_storm_data {
+/* Indicates if the Storm is enabled for fast debug recording (0/1) */
+ u8 fast_enabled;
+/* Fast debug Storm mode, valid only if fast_enabled is set */
+ u8 fast_mode;
+/* Indicates if the Storm is enabled for slow debug recording (0/1) */
+ u8 slow_enabled;
+/* Slow debug Storm mode, valid only if slow_enabled is set */
+ u8 slow_mode;
+ u8 hw_id /* HW ID associated with the Storm */;
+ u8 eid_filter_en /* Indicates if EID filtering is performed (0/1) */;
+/* 1 = EID range filter, 0 = EID mask filter. Valid only if eid_filter_en is
+ * set,
+ */
+ u8 eid_range_not_mask;
+ u8 cid_filter_en /* Indicates if CID filtering is performed (0/1) */;
+/* EID filter params to filter on. Valid only if eid_filter_en is set. */
+ union dbg_bus_storm_eid_params eid_filter_params;
+ __le16 reserved;
+/* CID to filter on. Valid only if cid_filter_en is set. */
+ __le32 cid;
+};
+
+/*
+ * Debug Bus data
+ */
+struct dbg_bus_data {
+ __le32 app_version /* The tools version number of the application */;
+ u8 state /* The current debug bus state */;
+ u8 hw_dwords /* HW dwords per cycle */;
+ u8 next_hw_id /* Next HW ID to be associated with an input */;
+ u8 num_enabled_blocks /* Number of blocks enabled for recording */;
+ u8 num_enabled_storms /* Number of Storms enabled for recording */;
+ u8 target /* Output target */;
+ u8 next_trigger_state /* ID of next trigger state to be added */;
+/* ID of next filter/trigger constraint to be added */
+ u8 next_constraint_id;
+ u8 one_shot_en /* Indicates if one-shot mode is enabled (0/1) */;
+ u8 grc_input_en /* Indicates if GRC recording is enabled (0/1) */;
+/* Indicates if timestamp recording is enabled (0/1) */
+ u8 timestamp_input_en;
+ u8 filter_en /* Indicates if the recording filter is enabled (0/1) */;
+/* Indicates if the recording trigger is enabled (0/1) */
+ u8 trigger_en;
+/* If true, the next added constraint belong to the filter. Otherwise,
+ * it belongs to the last added trigger state. Valid only if either filter or
+ * triggers are enabled.
+ */
+ u8 adding_filter;
+/* Indicates if the recording filter should be applied before the trigger.
+ * Valid only if both filter and trigger are enabled (0/1)
+ */
+ u8 filter_pre_trigger;
+/* Indicates if the recording filter should be applied after the trigger.
+ * Valid only if both filter and trigger are enabled (0/1)
+ */
+ u8 filter_post_trigger;
+/* If true, all inputs are associated with HW ID 0. Otherwise, each input is
+ * assigned a different HW ID (0/1)
+ */
+ u8 unify_inputs;
+/* Indicates if the other engine sends it NW recording to this engine (0/1) */
+ u8 rcv_from_other_engine;
+/* Debug Bus PCI buffer data. Valid only when the target is
+ * DBG_BUS_TARGET_ID_PCI.
+ */
+ struct dbg_bus_pci_buf_data pci_buf;
+ __le16 reserved;
+/* Debug Bus data for each block */
+ struct dbg_bus_block_data blocks[80];
+/* Debug Bus data for each block */
+ struct dbg_bus_storm_data storms[6];
+};
+
+
+/*
+ * Debug bus filter types
+ */
+enum dbg_bus_filter_types {
+ DBG_BUS_FILTER_TYPE_OFF /* filter always off */,
+ DBG_BUS_FILTER_TYPE_PRE /* filter before trigger only */,
+ DBG_BUS_FILTER_TYPE_POST /* filter after trigger only */,
+ DBG_BUS_FILTER_TYPE_ON /* filter always on */,
+ MAX_DBG_BUS_FILTER_TYPES
+};
+
+
+/*
+ * Debug bus frame modes
+ */
+enum dbg_bus_frame_modes {
+ DBG_BUS_FRAME_MODE_0HW_4ST = 0 /* 0 HW dwords, 4 Storm dwords */,
+ DBG_BUS_FRAME_MODE_4HW_0ST = 3 /* 4 HW dwords, 0 Storm dwords */,
+ DBG_BUS_FRAME_MODE_8HW_0ST = 4 /* 8 HW dwords, 0 Storm dwords */,
+ MAX_DBG_BUS_FRAME_MODES
+};
+
+
+/*
+ * Debug bus input types
+ */
+enum dbg_bus_input_types {
+ DBG_BUS_INPUT_TYPE_STORM,
+ DBG_BUS_INPUT_TYPE_BLOCK,
+ MAX_DBG_BUS_INPUT_TYPES
+};
+
+
+
+/*
+ * Debug bus other engine mode
+ */
+enum dbg_bus_other_engine_modes {
+ DBG_BUS_OTHER_ENGINE_MODE_NONE,
+ DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX,
+ DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX,
+ DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX,
+ DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX,
+ MAX_DBG_BUS_OTHER_ENGINE_MODES
+};
+
+
+
+/*
+ * Debug bus post-trigger recording types
+ */
+enum dbg_bus_post_trigger_types {
+ DBG_BUS_POST_TRIGGER_RECORD /* start recording after trigger */,
+ DBG_BUS_POST_TRIGGER_DROP /* drop data after trigger */,
+ MAX_DBG_BUS_POST_TRIGGER_TYPES
+};
+
+
+/*
+ * Debug bus pre-trigger recording types
+ */
+enum dbg_bus_pre_trigger_types {
+ DBG_BUS_PRE_TRIGGER_START_FROM_ZERO /* start recording from time 0 */,
+/* start recording some chunks before trigger */
+ DBG_BUS_PRE_TRIGGER_NUM_CHUNKS,
+ DBG_BUS_PRE_TRIGGER_DROP /* drop data before trigger */,
+ MAX_DBG_BUS_PRE_TRIGGER_TYPES
+};
+
+
+/*
+ * Debug bus SEMI frame modes
+ */
+enum dbg_bus_semi_frame_modes {
+/* 0 slow dwords, 4 fast dwords */
+ DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST = 0,
+/* 4 slow dwords, 0 fast dwords */
+ DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST = 3,
+ MAX_DBG_BUS_SEMI_FRAME_MODES
+};
+
+
+/*
+ * Debug bus states
+ */
+enum dbg_bus_states {
+ DBG_BUS_STATE_IDLE /* debug bus idle state (not recording) */,
+/* debug bus is ready for configuration and recording */
+ DBG_BUS_STATE_READY,
+ DBG_BUS_STATE_RECORDING /* debug bus is currently recording */,
+ DBG_BUS_STATE_STOPPED /* debug bus recording has stopped */,
+ MAX_DBG_BUS_STATES
+};
+
+
+
+
+
+
+/*
+ * Debug Bus Storm modes
+ */
+enum dbg_bus_storm_modes {
+ DBG_BUS_STORM_MODE_PRINTF /* store data (fast debug) */,
+ DBG_BUS_STORM_MODE_PRAM_ADDR /* pram address (fast debug) */,
+ DBG_BUS_STORM_MODE_DRA_RW /* DRA read/write data (fast debug) */,
+ DBG_BUS_STORM_MODE_DRA_W /* DRA write data (fast debug) */,
+ DBG_BUS_STORM_MODE_LD_ST_ADDR /* load/store address (fast debug) */,
+ DBG_BUS_STORM_MODE_DRA_FSM /* DRA state machines (fast debug) */,
+ DBG_BUS_STORM_MODE_RH /* recording handlers (fast debug) */,
+ DBG_BUS_STORM_MODE_FOC /* FOC: FIN + DRA Rd (slow debug) */,
+ DBG_BUS_STORM_MODE_EXT_STORE /* FOC: External Store (slow) */,
+ MAX_DBG_BUS_STORM_MODES
+};
+
+
+/*
+ * Debug bus target IDs
+ */
+enum dbg_bus_targets {
+/* records debug bus to DBG block internal buffer */
+ DBG_BUS_TARGET_ID_INT_BUF,
+ DBG_BUS_TARGET_ID_NIG /* records debug bus to the NW */,
+ DBG_BUS_TARGET_ID_PCI /* records debug bus to a PCI buffer */,
+ MAX_DBG_BUS_TARGETS
+};
+
+
+/*
+ * GRC Dump data
+ */
+struct dbg_grc_data {
+/* Value of each GRC parameter. Array size must match enum dbg_grc_params. */
+ __le32 param_val[40];
+/* Indicates for each GRC parameter if it was set by the user (0/1).
+ * Array size must match the enum dbg_grc_params.
+ */
+ u8 param_set_by_user[40];
+};
+
+
+/*
+ * Debug GRC params
+ */
+enum dbg_grc_params {
+ DBG_GRC_PARAM_DUMP_TSTORM /* dump Tstorm memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_MSTORM /* dump Mstorm memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_USTORM /* dump Ustorm memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_XSTORM /* dump Xstorm memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_YSTORM /* dump Ystorm memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_PSTORM /* dump Pstorm memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_REGS /* dump non-memory registers (0/1) */,
+ DBG_GRC_PARAM_DUMP_RAM /* dump Storm internal RAMs (0/1) */,
+ DBG_GRC_PARAM_DUMP_PBUF /* dump Storm passive buffer (0/1) */,
+ DBG_GRC_PARAM_DUMP_IOR /* dump Storm IORs (0/1) */,
+ DBG_GRC_PARAM_DUMP_VFC /* dump VFC memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_CM_CTX /* dump CM contexts (0/1) */,
+ DBG_GRC_PARAM_DUMP_PXP /* dump PXP memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_RSS /* dump RSS memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_CAU /* dump CAU memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_QM /* dump QM memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_MCP /* dump MCP memories (0/1) */,
+ DBG_GRC_PARAM_RESERVED /* reserved */,
+ DBG_GRC_PARAM_DUMP_CFC /* dump CFC memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_IGU /* dump IGU memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_BRB /* dump BRB memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_BTB /* dump BTB memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_BMB /* dump BMB memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_NIG /* dump NIG memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_MULD /* dump MULD memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_PRS /* dump PRS memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_DMAE /* dump PRS memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_TM /* dump TM (timers) memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_SDM /* dump SDM memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_DIF /* dump DIF memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_STATIC /* dump static debug data (0/1) */,
+ DBG_GRC_PARAM_UNSTALL /* un-stall Storms after dump (0/1) */,
+ DBG_GRC_PARAM_NUM_LCIDS /* number of LCIDs (0..320) */,
+ DBG_GRC_PARAM_NUM_LTIDS /* number of LTIDs (0..320) */,
+/* preset: exclude all memories from dump (1 only) */
+ DBG_GRC_PARAM_EXCLUDE_ALL,
+/* preset: include memories for crash dump (1 only) */
+ DBG_GRC_PARAM_CRASH,
+/* perform dump only if MFW is responding (0/1) */
+ DBG_GRC_PARAM_PARITY_SAFE,
+ DBG_GRC_PARAM_DUMP_CM /* dump CM memories (0/1) */,
+ DBG_GRC_PARAM_DUMP_PHY /* dump PHY memories (0/1) */,
+ MAX_DBG_GRC_PARAMS
+};
+
+
+/*
+ * Debug reset registers
+ */
+enum dbg_reset_regs {
+ DBG_RESET_REG_MISCS_PL_UA,
+ DBG_RESET_REG_MISCS_PL_HV,
+ DBG_RESET_REG_MISCS_PL_HV_2,
+ DBG_RESET_REG_MISC_PL_UA,
+ DBG_RESET_REG_MISC_PL_HV,
+ DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
+ DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
+ DBG_RESET_REG_MISC_PL_PDA_VAUX,
+ MAX_DBG_RESET_REGS
+};
+
+
+/*
+ * Debug status codes
+ */
+enum dbg_status {
+ DBG_STATUS_OK,
+ DBG_STATUS_APP_VERSION_NOT_SET,
+ DBG_STATUS_UNSUPPORTED_APP_VERSION,
+ DBG_STATUS_DBG_BLOCK_NOT_RESET,
+ DBG_STATUS_INVALID_ARGS,
+ DBG_STATUS_OUTPUT_ALREADY_SET,
+ DBG_STATUS_INVALID_PCI_BUF_SIZE,
+ DBG_STATUS_PCI_BUF_ALLOC_FAILED,
+ DBG_STATUS_PCI_BUF_NOT_ALLOCATED,
+ DBG_STATUS_TOO_MANY_INPUTS,
+ DBG_STATUS_INPUT_OVERLAP,
+ DBG_STATUS_HW_ONLY_RECORDING,
+ DBG_STATUS_STORM_ALREADY_ENABLED,
+ DBG_STATUS_STORM_NOT_ENABLED,
+ DBG_STATUS_BLOCK_ALREADY_ENABLED,
+ DBG_STATUS_BLOCK_NOT_ENABLED,
+ DBG_STATUS_NO_INPUT_ENABLED,
+ DBG_STATUS_NO_FILTER_TRIGGER_64B,
+ DBG_STATUS_FILTER_ALREADY_ENABLED,
+ DBG_STATUS_TRIGGER_ALREADY_ENABLED,
+ DBG_STATUS_TRIGGER_NOT_ENABLED,
+ DBG_STATUS_CANT_ADD_CONSTRAINT,
+ DBG_STATUS_TOO_MANY_TRIGGER_STATES,
+ DBG_STATUS_TOO_MANY_CONSTRAINTS,
+ DBG_STATUS_RECORDING_NOT_STARTED,
+ DBG_STATUS_DATA_DIDNT_TRIGGER,
+ DBG_STATUS_NO_DATA_RECORDED,
+ DBG_STATUS_DUMP_BUF_TOO_SMALL,
+ DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED,
+ DBG_STATUS_UNKNOWN_CHIP,
+ DBG_STATUS_VIRT_MEM_ALLOC_FAILED,
+ DBG_STATUS_BLOCK_IN_RESET,
+ DBG_STATUS_INVALID_TRACE_SIGNATURE,
+ DBG_STATUS_INVALID_NVRAM_BUNDLE,
+ DBG_STATUS_NVRAM_GET_IMAGE_FAILED,
+ DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE,
+ DBG_STATUS_NVRAM_READ_FAILED,
+ DBG_STATUS_IDLE_CHK_PARSE_FAILED,
+ DBG_STATUS_MCP_TRACE_BAD_DATA,
+ DBG_STATUS_MCP_TRACE_NO_META,
+ DBG_STATUS_MCP_COULD_NOT_HALT,
+ DBG_STATUS_MCP_COULD_NOT_RESUME,
+ DBG_STATUS_DMAE_FAILED,
+ DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
+ DBG_STATUS_IGU_FIFO_BAD_DATA,
+ DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
+ DBG_STATUS_FW_ASSERTS_PARSE_FAILED,
+ DBG_STATUS_REG_FIFO_BAD_DATA,
+ DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
+ DBG_STATUS_DBG_ARRAY_NOT_SET,
+ DBG_STATUS_MULTI_BLOCKS_WITH_FILTER,
+ MAX_DBG_STATUS
+};
+
+
+/*
+ * Debug Storms IDs
+ */
+enum dbg_storms {
+ DBG_TSTORM_ID,
+ DBG_MSTORM_ID,
+ DBG_USTORM_ID,
+ DBG_XSTORM_ID,
+ DBG_YSTORM_ID,
+ DBG_PSTORM_ID,
+ MAX_DBG_STORMS
+};
+
+
+/*
+ * Idle Check data
+ */
+struct idle_chk_data {
+ __le32 buf_size /* Idle check buffer size in dwords */;
+/* Indicates if the idle check buffer size was set (0/1) */
+ u8 buf_size_set;
+ u8 reserved1;
+ __le16 reserved2;
+};
+
+/*
+ * Debug Tools data (per HW function)
+ */
+struct dbg_tools_data {
+ struct dbg_grc_data grc /* GRC Dump data */;
+ struct dbg_bus_data bus /* Debug Bus data */;
+ struct idle_chk_data idle_chk /* Idle Check data */;
+ u8 mode_enable[40] /* Indicates if a mode is enabled (0/1) */;
+/* Indicates if a block is in reset state (0/1) */
+ u8 block_in_reset[80];
+ u8 chip_id /* Chip ID (from enum chip_ids) */;
+ u8 platform_id /* Platform ID (from enum platform_ids) */;
+ u8 initialized /* Indicates if the data was initialized */;
+ u8 reserved;
+};
+
+
+#endif /* __ECORE_HSI_DEBUG_TOOLS__ */
--- /dev/null
+/*
+ * Copyright (c) 2016 QLogic Corporation.
+ * All rights reserved.
+ * www.qlogic.com
+ *
+ * See LICENSE.qede_pmd for copyright and licensing details.
+ */
+
+#ifndef __ECORE_HSI_INIT_FUNC__
+#define __ECORE_HSI_INIT_FUNC__
+/********************************/
+/* HSI Init Functions constants */
+/********************************/
+
+/* Number of VLAN priorities */
+#define NUM_OF_VLAN_PRIORITIES 8
+
+
+/*
+ * BRB RAM init requirements
+ */
+struct init_brb_ram_req {
+ __le32 guranteed_per_tc /* guaranteed size per TC, in bytes */;
+ __le32 headroom_per_tc /* headroom size per TC, in bytes */;
+ __le32 min_pkt_size /* min packet size, in bytes */;
+ __le32 max_ports_per_engine /* min packet size, in bytes */;
+ u8 num_active_tcs[MAX_NUM_PORTS] /* number of active TCs per port */;
+};
+
+
+/*
+ * ETS per-TC init requirements
+ */
+struct init_ets_tc_req {
+/* if set, this TC participates in the arbitration with a strict priority
+ * (the priority is equal to the TC ID)
+ */
+ u8 use_sp;
+/* if set, this TC participates in the arbitration with a WFQ weight
+ * (indicated by the weight field)
+ */
+ u8 use_wfq;
+/* An arbitration weight. Valid only if use_wfq is set. */
+ __le16 weight;
+};
+
+/*
+ * ETS init requirements
+ */
+struct init_ets_req {
+ __le32 mtu /* Max packet size (in bytes) */;
+/* ETS initialization requirements per TC. */
+ struct init_ets_tc_req tc_req[NUM_OF_TCS];
+};
+
+
+
+/*
+ * NIG LB RL init requirements
+ */
+struct init_nig_lb_rl_req {
+/* Global MAC+LB RL rate (in Mbps). If set to 0, the RL will be disabled. */
+ __le16 lb_mac_rate;
+/* Global LB RL rate (in Mbps). If set to 0, the RL will be disabled. */
+ __le16 lb_rate;
+ __le32 mtu /* Max packet size (in bytes) */;
+/* RL rate per physical TC (in Mbps). If set to 0, the RL will be disabled. */
+ __le16 tc_rate[NUM_OF_PHYS_TCS];
+};
+
+
+/*
+ * NIG TC mapping for each priority
+ */
+struct init_nig_pri_tc_map_entry {
+ u8 tc_id /* the mapped TC ID */;
+ u8 valid /* indicates if the mapping entry is valid */;
+};
+
+
+/*
+ * NIG priority to TC map init requirements
+ */
+struct init_nig_pri_tc_map_req {
+ struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
+};
+
+
+/*
+ * QM per-port init parameters
+ */
+struct init_qm_port_params {
+ u8 active /* Indicates if this port is active */;
+/* Vector of valid bits for active TCs used by this port */
+ u8 active_phys_tcs;
+/* number of PBF command lines that can be used by this port */
+ __le16 num_pbf_cmd_lines;
+/* number of BTB blocks that can be used by this port */
+ __le16 num_btb_blocks;
+ __le16 reserved;
+};
+
+
+/*
+ * QM per-PQ init parameters
+ */
+struct init_qm_pq_params {
+ u8 vport_id /* VPORT ID */;
+ u8 tc_id /* TC ID */;
+ u8 wrr_group /* WRR group */;
+/* Indicates if a rate limiter should be allocated for the PQ (0/1) */
+ u8 rl_valid;
+};
+
+
+/*
+ * QM per-vport init parameters
+ */
+struct init_qm_vport_params {
+/* rate limit in Mb/sec units. a value of 0 means dont configure. ignored if
+ * VPORT RL is globally disabled.
+ */
+ __le32 vport_rl;
+/* WFQ weight. A value of 0 means dont configure. ignored if VPORT WFQ is
+ * globally disabled.
+ */
+ __le16 vport_wfq;
+/* the first Tx PQ ID associated with this VPORT for each TC. */
+ __le16 first_tx_pq_id[NUM_OF_TCS];
+};
+
+#endif /* __ECORE_HSI_INIT_FUNC__ */
--- /dev/null
+/*
+ * Copyright (c) 2016 QLogic Corporation.
+ * All rights reserved.
+ * www.qlogic.com
+ *
+ * See LICENSE.qede_pmd for copyright and licensing details.
+ */
+
+#ifndef __ECORE_HSI_INIT_TOOL__
+#define __ECORE_HSI_INIT_TOOL__
+/**************************************/
+/* Init Tool HSI constants and macros */
+/**************************************/
+
+/* Width of GRC address in bits (addresses are specified in dwords) */
+#define GRC_ADDR_BITS 23
+#define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1)
+
+/* indicates an init that should be applied to any phase ID */
+#define ANY_PHASE_ID 0xffff
+
+/* Max size in dwords of a zipped array */
+#define MAX_ZIPPED_SIZE 8192
+
+
+struct fw_asserts_ram_section {
+/* The offset of the section in the RAM in RAM lines (64-bit units) */
+ __le16 section_ram_line_offset;
+/* The size of the section in RAM lines (64-bit units) */
+ __le16 section_ram_line_size;
+/* The offset of the asserts list within the section in dwords */
+ u8 list_dword_offset;
+/* The size of an assert list element in dwords */
+ u8 list_element_dword_size;
+ u8 list_num_elements /* The number of elements in the asserts list */;
+/* The offset of the next list index field within the section in dwords */
+ u8 list_next_index_dword_offset;
+};
+
+
+struct fw_ver_num {
+ u8 major /* Firmware major version number */;
+ u8 minor /* Firmware minor version number */;
+ u8 rev /* Firmware revision version number */;
+/* Firmware engineering version number (for bootleg versions) */
+ u8 eng;
+};
+
+struct fw_ver_info {
+ __le16 tools_ver /* Tools version number */;
+ u8 image_id /* FW image ID (e.g. main, l2b, kuku) */;
+ u8 reserved1;
+ struct fw_ver_num num /* FW version number */;
+ __le32 timestamp /* FW Timestamp in unix time (sec. since 1970) */;
+ __le32 reserved2;
+};
+
+struct fw_info {
+ struct fw_ver_info ver /* FW version information */;
+/* Info regarding the FW asserts section in the Storm RAM */
+ struct fw_asserts_ram_section fw_asserts_section;
+};
+
+
+struct fw_info_location {
+/* GRC address where the fw_info struct is located. */
+ __le32 grc_addr;
+/* Size of the fw_info structure (thats located at the grc_addr). */
+ __le32 size;
+};
+
+
+
+
+enum init_modes {
+ MODE_BB_A0,
+ MODE_BB_B0,
+ MODE_K2,
+ MODE_ASIC,
+ MODE_EMUL_REDUCED,
+ MODE_EMUL_FULL,
+ MODE_FPGA,
+ MODE_CHIPSIM,
+ MODE_SF,
+ MODE_MF_SD,
+ MODE_MF_SI,
+ MODE_PORTS_PER_ENG_1,
+ MODE_PORTS_PER_ENG_2,
+ MODE_PORTS_PER_ENG_4,
+ MODE_100G,
+ MODE_40G,
+ MODE_EAGLE_ENG1_WORKAROUND,
+ MAX_INIT_MODES
+};
+
+
+enum init_phases {
+ PHASE_ENGINE,
+ PHASE_PORT,
+ PHASE_PF,
+ PHASE_VF,
+ PHASE_QM_PF,
+ MAX_INIT_PHASES
+};
+
+
+enum init_split_types {
+ SPLIT_TYPE_NONE,
+ SPLIT_TYPE_PORT,
+ SPLIT_TYPE_PF,
+ SPLIT_TYPE_PORT_PF,
+ SPLIT_TYPE_VF,
+ MAX_INIT_SPLIT_TYPES
+};
+
+
+/*
+ * Binary buffer header
+ */
+struct bin_buffer_hdr {
+/* buffer offset in bytes from the beginning of the binary file */
+ __le32 offset;
+ __le32 length /* buffer length in bytes */;
+};
+
+
+/*
+ * binary init buffer types
+ */
+enum bin_init_buffer_type {
+ BIN_BUF_INIT_FW_VER_INFO /* fw_ver_info struct */,
+ BIN_BUF_INIT_CMD /* init commands */,
+ BIN_BUF_INIT_VAL /* init data */,
+ BIN_BUF_INIT_MODE_TREE /* init modes tree */,
+ BIN_BUF_INIT_IRO /* internal RAM offsets */,
+ MAX_BIN_INIT_BUFFER_TYPE
+};
+
+
+/*
+ * init array header: raw
+ */
+struct init_array_raw_hdr {
+ __le32 data;
+/* Init array type, from init_array_types enum */
+#define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
+#define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
+/* init array params */
+#define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF
+#define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
+};
+
+/*
+ * init array header: standard
+ */
+struct init_array_standard_hdr {
+ __le32 data;
+/* Init array type, from init_array_types enum */
+#define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
+#define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
+/* Init array size (in dwords) */
+#define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
+#define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
+};
+
+/*
+ * init array header: zipped
+ */
+struct init_array_zipped_hdr {
+ __le32 data;
+/* Init array type, from init_array_types enum */
+#define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
+#define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
+/* Init array zipped size (in bytes) */
+#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
+#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
+};
+
+/*
+ * init array header: pattern
+ */
+struct init_array_pattern_hdr {
+ __le32 data;
+/* Init array type, from init_array_types enum */
+#define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
+#define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
+/* pattern size in dword */
+#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
+#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
+/* pattern repetitions */
+#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
+#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8
+};
+
+/*
+ * init array header union
+ */
+union init_array_hdr {
+ struct init_array_raw_hdr raw /* raw init array header */;
+/* standard init array header */
+ struct init_array_standard_hdr standard;
+ struct init_array_zipped_hdr zipped /* zipped init array header */;
+ struct init_array_pattern_hdr pattern /* pattern init array header */;
+};
+
+
+
+
+
+/*
+ * init array types
+ */
+enum init_array_types {
+ INIT_ARR_STANDARD /* standard init array */,
+ INIT_ARR_ZIPPED /* zipped init array */,
+ INIT_ARR_PATTERN /* a repeated pattern */,
+ MAX_INIT_ARRAY_TYPES
+};
+
+
+
+/*
+ * init operation: callback
+ */
+struct init_callback_op {
+ __le32 op_data;
+/* Init operation, from init_op_types enum */
+#define INIT_CALLBACK_OP_OP_MASK 0xF
+#define INIT_CALLBACK_OP_OP_SHIFT 0
+#define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
+#define INIT_CALLBACK_OP_RESERVED_SHIFT 4
+ __le16 callback_id /* Callback ID */;
+ __le16 block_id /* Blocks ID */;
+};
+
+
+/*
+ * init operation: delay
+ */
+struct init_delay_op {
+ __le32 op_data;
+/* Init operation, from init_op_types enum */
+#define INIT_DELAY_OP_OP_MASK 0xF
+#define INIT_DELAY_OP_OP_SHIFT 0
+#define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
+#define INIT_DELAY_OP_RESERVED_SHIFT 4
+ __le32 delay /* delay in us */;
+};
+
+
+/*
+ * init operation: if_mode
+ */
+struct init_if_mode_op {
+ __le32 op_data;
+/* Init operation, from init_op_types enum */
+#define INIT_IF_MODE_OP_OP_MASK 0xF
+#define INIT_IF_MODE_OP_OP_SHIFT 0
+#define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
+#define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
+/* Commands to skip if the modes dont match */
+#define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
+#define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
+ __le16 reserved2;
+/* offset (in bytes) in modes expression buffer */
+ __le16 modes_buf_offset;
+};
+
+
+/*
+ * init operation: if_phase
+ */
+struct init_if_phase_op {
+ __le32 op_data;
+/* Init operation, from init_op_types enum */
+#define INIT_IF_PHASE_OP_OP_MASK 0xF
+#define INIT_IF_PHASE_OP_OP_SHIFT 0
+/* Indicates if DMAE is enabled in this phase */
+#define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1
+#define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
+#define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF
+#define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5
+/* Commands to skip if the phases dont match */
+#define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
+#define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
+ __le32 phase_data;
+#define INIT_IF_PHASE_OP_PHASE_MASK 0xFF /* Init phase */
+#define INIT_IF_PHASE_OP_PHASE_SHIFT 0
+#define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
+#define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
+#define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF /* Init phase ID */
+#define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
+};
+
+
+/*
+ * init mode operators
+ */
+enum init_mode_ops {
+ INIT_MODE_OP_NOT /* init mode not operator */,
+ INIT_MODE_OP_OR /* init mode or operator */,
+ INIT_MODE_OP_AND /* init mode and operator */,
+ MAX_INIT_MODE_OPS
+};
+
+
+/*
+ * init operation: raw
+ */
+struct init_raw_op {
+ __le32 op_data;
+/* Init operation, from init_op_types enum */
+#define INIT_RAW_OP_OP_MASK 0xF
+#define INIT_RAW_OP_OP_SHIFT 0
+#define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF /* init param 1 */
+#define INIT_RAW_OP_PARAM1_SHIFT 4
+ __le32 param2 /* Init param 2 */;
+};
+
+/*
+ * init array params
+ */
+struct init_op_array_params {
+ __le16 size /* array size in dwords */;
+ __le16 offset /* array start offset in dwords */;
+};
+
+/*
+ * Write init operation arguments
+ */
+union init_write_args {
+/* value to write, used when init source is INIT_SRC_INLINE */
+ __le32 inline_val;
+/* number of zeros to write, used when init source is INIT_SRC_ZEROS */
+ __le32 zeros_count;
+/* array offset to write, used when init source is INIT_SRC_ARRAY */
+ __le32 array_offset;
+/* runtime array params to write, used when init source is INIT_SRC_RUNTIME */
+ struct init_op_array_params runtime;
+};
+
+/*
+ * init operation: write
+ */
+struct init_write_op {
+ __le32 data;
+/* init operation, from init_op_types enum */
+#define INIT_WRITE_OP_OP_MASK 0xF
+#define INIT_WRITE_OP_OP_SHIFT 0
+/* init source type, taken from init_source_types enum */
+#define INIT_WRITE_OP_SOURCE_MASK 0x7
+#define INIT_WRITE_OP_SOURCE_SHIFT 4
+#define INIT_WRITE_OP_RESERVED_MASK 0x1
+#define INIT_WRITE_OP_RESERVED_SHIFT 7
+/* indicates if the register is wide-bus */
+#define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
+#define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
+/* internal (absolute) GRC address, in dwords */
+#define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
+#define INIT_WRITE_OP_ADDRESS_SHIFT 9
+ union init_write_args args /* Write init operation arguments */;
+};
+
+/*
+ * init operation: read
+ */
+struct init_read_op {
+ __le32 op_data;
+/* init operation, from init_op_types enum */
+#define INIT_READ_OP_OP_MASK 0xF
+#define INIT_READ_OP_OP_SHIFT 0
+/* polling type, from init_poll_types enum */
+#define INIT_READ_OP_POLL_TYPE_MASK 0xF
+#define INIT_READ_OP_POLL_TYPE_SHIFT 4
+#define INIT_READ_OP_RESERVED_MASK 0x1
+#define INIT_READ_OP_RESERVED_SHIFT 8
+/* internal (absolute) GRC address, in dwords */
+#define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
+#define INIT_READ_OP_ADDRESS_SHIFT 9
+/* expected polling value, used only when polling is done */
+ __le32 expected_val;
+};
+
+/*
+ * Init operations union
+ */
+union init_op {
+ struct init_raw_op raw /* raw init operation */;
+ struct init_write_op write /* write init operation */;
+ struct init_read_op read /* read init operation */;
+ struct init_if_mode_op if_mode /* if_mode init operation */;
+ struct init_if_phase_op if_phase /* if_phase init operation */;
+ struct init_callback_op callback /* callback init operation */;
+ struct init_delay_op delay /* delay init operation */;
+};
+
+
+
+/*
+ * Init command operation types
+ */
+enum init_op_types {
+ INIT_OP_READ /* GRC read init command */,
+ INIT_OP_WRITE /* GRC write init command */,
+/* Skip init commands if the init modes expression doesn't match */
+ INIT_OP_IF_MODE,
+/* Skip init commands if the init phase doesn't match */
+ INIT_OP_IF_PHASE,
+ INIT_OP_DELAY /* delay init command */,
+ INIT_OP_CALLBACK /* callback init command */,
+ MAX_INIT_OP_TYPES
+};
+
+
+/*
+ * init polling types
+ */
+enum init_poll_types {
+ INIT_POLL_NONE /* No polling */,
+ INIT_POLL_EQ /* init value is included in the init command */,
+ INIT_POLL_OR /* init value is all zeros */,
+ INIT_POLL_AND /* init value is an array of values */,
+ MAX_INIT_POLL_TYPES
+};
+
+
+
+
+/*
+ * init source types
+ */
+enum init_source_types {
+ INIT_SRC_INLINE /* init value is included in the init command */,
+ INIT_SRC_ZEROS /* init value is all zeros */,
+ INIT_SRC_ARRAY /* init value is an array of values */,
+ INIT_SRC_RUNTIME /* init value is provided during runtime */,
+ MAX_INIT_SOURCE_TYPES
+};
+
+
+
+
+/*
+ * Internal RAM Offsets macro data
+ */
+struct iro {
+ __le32 base /* RAM field offset */;
+ __le16 m1 /* multiplier 1 */;
+ __le16 m2 /* multiplier 2 */;
+ __le16 m3 /* multiplier 3 */;
+ __le16 size /* RAM field size */;
+};
+
+#endif /* __ECORE_HSI_INIT_TOOL__ */
+++ /dev/null
-/*
- * Copyright (c) 2016 QLogic Corporation.
- * All rights reserved.
- * www.qlogic.com
- *
- * See LICENSE.qede_pmd for copyright and licensing details.
- */
-
-#ifndef __ECORE_HSI_TOOLS__
-#define __ECORE_HSI_TOOLS__
-/**********************************/
-/* Tools HSI constants and macros */
-/**********************************/
-
-/*********************************** Init ************************************/
-
-/* Width of GRC address in bits (addresses are specified in dwords) */
-#define GRC_ADDR_BITS 23
-#define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1)
-
-/* indicates an init that should be applied to any phase ID */
-#define ANY_PHASE_ID 0xffff
-
-/* init pattern size in bytes */
-#define INIT_PATTERN_SIZE_BITS 4
-#define MAX_INIT_PATTERN_SIZE (1 << INIT_PATTERN_SIZE_BITS)
-
-/* Max size in dwords of a zipped array */
-#define MAX_ZIPPED_SIZE 8192
-
-/* Global PXP window */
-#define NUM_OF_PXP_WIN 19
-#define PXP_WIN_DWORD_SIZE_BITS 10
-#define PXP_WIN_DWORD_SIZE (1 << PXP_WIN_DWORD_SIZE_BITS)
-#define PXP_WIN_BYTE_SIZE_BITS (PXP_WIN_DWORD_SIZE_BITS + 2)
-#define PXP_WIN_BYTE_SIZE (PXP_WIN_DWORD_SIZE * 4)
-
-/********************************* GRC Dump **********************************/
-
-/* width of GRC dump register sequence length in bits */
-#define DUMP_SEQ_LEN_BITS 8
-#define DUMP_SEQ_LEN_MAX_VAL ((1 << DUMP_SEQ_LEN_BITS) - 1)
-
-/* width of GRC dump memory length in bits */
-#define DUMP_MEM_LEN_BITS 18
-#define DUMP_MEM_LEN_MAX_VAL ((1 << DUMP_MEM_LEN_BITS) - 1)
-
-/* width of register type ID in bits */
-#define REG_TYPE_ID_BITS 6
-#define REG_TYPE_ID_MAX_VAL ((1 << REG_TYPE_ID_BITS) - 1)
-
-/* width of block ID in bits */
-#define BLOCK_ID_BITS 8
-#define BLOCK_ID_MAX_VAL ((1 << BLOCK_ID_BITS) - 1)
-
-/******************************** Idle Check *********************************/
-
-/* max number of idle check predicate immediates */
-#define MAX_IDLE_CHK_PRED_IMM 3
-
-/* max number of idle check argument registers */
-#define MAX_IDLE_CHK_READ_REGS 3
-
-/* max number of idle check loops */
-#define MAX_IDLE_CHK_LOOPS 0x10000
-
-/* max idle check address increment */
-#define MAX_IDLE_CHK_INCREMENT 0x10000
-
-/* inicates an undefined idle check line index */
-#define IDLE_CHK_UNDEFINED_LINE_IDX 0xffffff
-
-/* max number of register values following the idle check header for LSI */
-#define IDLE_CHK_MAX_LSI_DUMP_REGS 2
-
-/* arguments for IDLE_CHK_MACRO_TYPE_QM_RD_WR */
-#define IDLE_CHK_QM_RD_WR_PTR 0
-#define IDLE_CHK_QM_RD_WR_BANK 1
-
-/**************************************/
-/* HSI Functions constants and macros */
-/**************************************/
-
-/* Number of VLAN priorities */
-#define NUM_OF_VLAN_PRIORITIES 8
-
-/* the MCP Trace meta data signautre is duplicated in the
- * perl script that generats the NVRAM images
- */
-#define MCP_TRACE_META_IMAGE_SIGNATURE 0x669955aa
-
-/* Maximal number of RAM lines occupied by FW Asserts data */
-#define MAX_FW_ASSERTS_RAM_LINES 800
-
-/*
- * Binary buffer header
- */
-struct bin_buffer_hdr {
- __le32 offset
- /* buffer offset in bytes from the beginning of the binary file */;
- __le32 length /* buffer length in bytes */;
-};
-
-/*
- * binary buffer types
- */
-enum bin_buffer_type {
- BIN_BUF_FW_VER_INFO /* fw_ver_info struct */,
- BIN_BUF_INIT_CMD /* init commands */,
- BIN_BUF_INIT_VAL /* init data */,
- BIN_BUF_INIT_MODE_TREE /* init modes tree */,
- BIN_BUF_IRO /* internal RAM offsets array */,
- MAX_BIN_BUFFER_TYPE
-};
-
-/*
- * Chip IDs
- */
-enum chip_ids {
- CHIP_BB_A0 /* BB A0 chip ID */,
- CHIP_BB_B0 /* BB B0 chip ID */,
- CHIP_K2 /* AH chip ID */,
- MAX_CHIP_IDS
-};
-
-/*
- * memory dump descriptor
- */
-struct dbg_dump_mem_desc {
- __le32 dword0;
-#define DBG_DUMP_MEM_DESC_ADDRESS_MASK 0xFFFFFF
-#define DBG_DUMP_MEM_DESC_ADDRESS_SHIFT 0
-#define DBG_DUMP_MEM_DESC_ASIC_CHIP_MASK_MASK 0xF
-#define DBG_DUMP_MEM_DESC_ASIC_CHIP_MASK_SHIFT 24
-#define DBG_DUMP_MEM_DESC_SIM_CHIP_MASK_MASK 0xF
-#define DBG_DUMP_MEM_DESC_SIM_CHIP_MASK_SHIFT 28
- __le32 dword1;
-#define DBG_DUMP_MEM_DESC_LENGTH_MASK 0x3FFFF
-#define DBG_DUMP_MEM_DESC_LENGTH_SHIFT 0
-#define DBG_DUMP_MEM_DESC_REG_TYPE_ID_MASK 0x3F
-#define DBG_DUMP_MEM_DESC_REG_TYPE_ID_SHIFT 18
-#define DBG_DUMP_MEM_DESC_BLOCK_ID_MASK 0xFF
-#define DBG_DUMP_MEM_DESC_BLOCK_ID_SHIFT 24
-};
-
-/*
- * registers dump descriptor: chip
- */
-struct dbg_dump_regs_chip_desc {
- __le32 data;
-#define DBG_DUMP_REGS_CHIP_DESC_IS_CHIP_MASK_MASK 0x1
-#define DBG_DUMP_REGS_CHIP_DESC_IS_CHIP_MASK_SHIFT 0
-#define DBG_DUMP_REGS_CHIP_DESC_ASIC_CHIP_MASK_MASK 0x7FFFFF
-#define DBG_DUMP_REGS_CHIP_DESC_ASIC_CHIP_MASK_SHIFT 1
-#define DBG_DUMP_REGS_CHIP_DESC_SIM_CHIP_MASK_MASK 0xFF
-#define DBG_DUMP_REGS_CHIP_DESC_SIM_CHIP_MASK_SHIFT 24
-};
-
-/*
- * registers dump descriptor: raw
- */
-struct dbg_dump_regs_raw_desc {
- __le32 data;
-#define DBG_DUMP_REGS_RAW_DESC_IS_CHIP_MASK_MASK 0x1
-#define DBG_DUMP_REGS_RAW_DESC_IS_CHIP_MASK_SHIFT 0
-#define DBG_DUMP_REGS_RAW_DESC_PARAM1_MASK 0x7FFFFF
-#define DBG_DUMP_REGS_RAW_DESC_PARAM1_SHIFT 1
-#define DBG_DUMP_REGS_RAW_DESC_PARAM2_MASK 0xFF
-#define DBG_DUMP_REGS_RAW_DESC_PARAM2_SHIFT 24
-};
-
-/*
- * registers dump descriptor: sequence
- */
-struct dbg_dump_regs_seq_desc {
- __le32 data;
-#define DBG_DUMP_REGS_SEQ_DESC_IS_CHIP_MASK_MASK 0x1
-#define DBG_DUMP_REGS_SEQ_DESC_IS_CHIP_MASK_SHIFT 0
-#define DBG_DUMP_REGS_SEQ_DESC_ADDRESS_MASK 0x7FFFFF
-#define DBG_DUMP_REGS_SEQ_DESC_ADDRESS_SHIFT 1
-#define DBG_DUMP_REGS_SEQ_DESC_LENGTH_MASK 0xFF
-#define DBG_DUMP_REGS_SEQ_DESC_LENGTH_SHIFT 24
-};
-
-/*
- * registers dump descriptor
- */
-union dbg_dump_regs_desc {
- struct dbg_dump_regs_raw_desc raw /* dumped registers raw descriptor */
- ;
- struct dbg_dump_regs_seq_desc seq /* dumped registers seq descriptor */
- ;
- struct dbg_dump_regs_chip_desc chip
- /* dumped registers chip descriptor */;
-};
-
-/*
- * idle check macro types
- */
-enum idle_chk_macro_types {
- IDLE_CHK_MACRO_TYPE_COMPARE /* parametric register comparison */,
- IDLE_CHK_MACRO_TYPE_QM_RD_WR /* compare QM r/w pointers and banks */,
- MAX_IDLE_CHK_MACRO_TYPES
-};
-
-/*
- * Idle Check result header
- */
-struct idle_chk_result_hdr {
- __le16 rule_idx /* Idle check rule index in CSV file */;
- __le16 loop_idx /* the loop index in which the failure occurred */;
- __le16 num_fw_values;
- __le16 data;
-#define IDLE_CHK_RESULT_HDR_NUM_LSI_VALUES_MASK 0xF
-#define IDLE_CHK_RESULT_HDR_NUM_LSI_VALUES_SHIFT 0
-#define IDLE_CHK_RESULT_HDR_LOOP_VALID_MASK 0x1
-#define IDLE_CHK_RESULT_HDR_LOOP_VALID_SHIFT 4
-#define IDLE_CHK_RESULT_HDR_SEVERITY_MASK 0x7
-#define IDLE_CHK_RESULT_HDR_SEVERITY_SHIFT 5
-#define IDLE_CHK_RESULT_HDR_MACRO_TYPE_MASK 0xF
-#define IDLE_CHK_RESULT_HDR_MACRO_TYPE_SHIFT 8
-#define IDLE_CHK_RESULT_HDR_MACRO_TYPE_ARG_MASK 0xF
-#define IDLE_CHK_RESULT_HDR_MACRO_TYPE_ARG_SHIFT 12
-};
-
-/*
- * Idle Check rule
- */
-struct idle_chk_rule {
- __le32 data;
-#define IDLE_CHK_RULE_ASIC_CHIP_MASK_MASK 0xF
-#define IDLE_CHK_RULE_ASIC_CHIP_MASK_SHIFT 0
-#define IDLE_CHK_RULE_SIM_CHIP_MASK_MASK 0xF
-#define IDLE_CHK_RULE_SIM_CHIP_MASK_SHIFT 4
-#define IDLE_CHK_RULE_BLOCK_ID_MASK 0xFF
-#define IDLE_CHK_RULE_BLOCK_ID_SHIFT 8
-#define IDLE_CHK_RULE_MACRO_TYPE_MASK 0xF
-#define IDLE_CHK_RULE_MACRO_TYPE_SHIFT 16
-#define IDLE_CHK_RULE_SEVERITY_MASK 0x7
-#define IDLE_CHK_RULE_SEVERITY_SHIFT 20
-#define IDLE_CHK_RULE_RESERVED_MASK 0x1
-#define IDLE_CHK_RULE_RESERVED_SHIFT 23
-#define IDLE_CHK_RULE_PRED_ID_MASK 0xFF
-#define IDLE_CHK_RULE_PRED_ID_SHIFT 24
- __le16 loop;
- __le16 increment
- /* address increment of first argument register on each iteration */
- ;
- __le32 reg_addr[3];
- __le32 pred_imm[3]
- /* immediate values passed as arguments to the idle check rule */;
-};
-
-/*
- * idle check severity types
- */
-enum idle_chk_severity_types {
- IDLE_CHK_SEVERITY_ERROR /* idle check failure should cause an error */,
- IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC
- ,
- IDLE_CHK_SEVERITY_WARNING
- /* idle check failure should cause a warning */,
- MAX_IDLE_CHK_SEVERITY_TYPES
-};
-
-/*
- * init array header: raw
- */
-struct init_array_raw_hdr {
- __le32 data;
-#define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
-#define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
-#define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF
-#define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
-};
-
-/*
- * init array header: standard
- */
-struct init_array_standard_hdr {
- __le32 data;
-#define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
-#define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
-#define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
-#define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
-};
-
-/*
- * init array header: zipped
- */
-struct init_array_zipped_hdr {
- __le32 data;
-#define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
-#define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
-#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
-#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
-};
-
-/*
- * init array header: pattern
- */
-struct init_array_pattern_hdr {
- __le32 data;
-#define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
-#define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
-#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
-#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
-#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
-#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8
-};
-
-/*
- * init array header union
- */
-union init_array_hdr {
- struct init_array_raw_hdr raw /* raw init array header */;
- struct init_array_standard_hdr standard /* standard init array header */
- ;
- struct init_array_zipped_hdr zipped /* zipped init array header */;
- struct init_array_pattern_hdr pattern /* pattern init array header */;
-};
-
-/*
- * init array types
- */
-enum init_array_types {
- INIT_ARR_STANDARD /* standard init array */,
- INIT_ARR_ZIPPED /* zipped init array */,
- INIT_ARR_PATTERN /* a repeated pattern */,
- MAX_INIT_ARRAY_TYPES
-};
-
-/*
- * init operation: callback
- */
-struct init_callback_op {
- __le32 op_data;
-#define INIT_CALLBACK_OP_OP_MASK 0xF
-#define INIT_CALLBACK_OP_OP_SHIFT 0
-#define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
-#define INIT_CALLBACK_OP_RESERVED_SHIFT 4
- __le16 callback_id /* Callback ID */;
- __le16 block_id /* Blocks ID */;
-};
-
-/*
- * init operation: delay
- */
-struct init_delay_op {
- __le32 op_data;
-#define INIT_DELAY_OP_OP_MASK 0xF
-#define INIT_DELAY_OP_OP_SHIFT 0
-#define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
-#define INIT_DELAY_OP_RESERVED_SHIFT 4
- __le32 delay /* delay in us */;
-};
-
-/*
- * init operation: if_mode
- */
-struct init_if_mode_op {
- __le32 op_data;
-#define INIT_IF_MODE_OP_OP_MASK 0xF
-#define INIT_IF_MODE_OP_OP_SHIFT 0
-#define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
-#define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
-#define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
-#define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
- __le16 reserved2;
- __le16 modes_buf_offset
- /* offset (in bytes) in modes expression buffer */;
-};
-
-/*
- * init operation: if_phase
- */
-struct init_if_phase_op {
- __le32 op_data;
-#define INIT_IF_PHASE_OP_OP_MASK 0xF
-#define INIT_IF_PHASE_OP_OP_SHIFT 0
-#define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1
-#define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
-#define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF
-#define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5
-#define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
-#define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
- __le32 phase_data;
-#define INIT_IF_PHASE_OP_PHASE_MASK 0xFF
-#define INIT_IF_PHASE_OP_PHASE_SHIFT 0
-#define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
-#define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
-#define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF
-#define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
-};
-
-/*
- * init mode operators
- */
-enum init_mode_ops {
- INIT_MODE_OP_NOT /* init mode not operator */,
- INIT_MODE_OP_OR /* init mode or operator */,
- INIT_MODE_OP_AND /* init mode and operator */,
- MAX_INIT_MODE_OPS
-};
-
-/*
- * init operation: raw
- */
-struct init_raw_op {
- __le32 op_data;
-#define INIT_RAW_OP_OP_MASK 0xF
-#define INIT_RAW_OP_OP_SHIFT 0
-#define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF
-#define INIT_RAW_OP_PARAM1_SHIFT 4
- __le32 param2 /* Init param 2 */;
-};
-
-/*
- * init array params
- */
-struct init_op_array_params {
- __le16 size /* array size in dwords */;
- __le16 offset /* array start offset in dwords */;
-};
-
-/*
- * Write init operation arguments
- */
-union init_write_args {
- __le32 inline_val
- /* value to write, used when init source is INIT_SRC_INLINE */;
- __le32 zeros_count;
- __le32 array_offset
- /* array offset to write, used when init source is INIT_SRC_ARRAY */
- ;
- struct init_op_array_params runtime;
-};
-
-/*
- * init operation: write
- */
-struct init_write_op {
- __le32 data;
-#define INIT_WRITE_OP_OP_MASK 0xF
-#define INIT_WRITE_OP_OP_SHIFT 0
-#define INIT_WRITE_OP_SOURCE_MASK 0x7
-#define INIT_WRITE_OP_SOURCE_SHIFT 4
-#define INIT_WRITE_OP_RESERVED_MASK 0x1
-#define INIT_WRITE_OP_RESERVED_SHIFT 7
-#define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
-#define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
-#define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
-#define INIT_WRITE_OP_ADDRESS_SHIFT 9
- union init_write_args args /* Write init operation arguments */;
-};
-
-/*
- * init operation: read
- */
-struct init_read_op {
- __le32 op_data;
-#define INIT_READ_OP_OP_MASK 0xF
-#define INIT_READ_OP_OP_SHIFT 0
-#define INIT_READ_OP_POLL_TYPE_MASK 0xF
-#define INIT_READ_OP_POLL_TYPE_SHIFT 4
-#define INIT_READ_OP_RESERVED_MASK 0x1
-#define INIT_READ_OP_RESERVED_SHIFT 8
-#define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
-#define INIT_READ_OP_ADDRESS_SHIFT 9
- __le32 expected_val
- /* expected polling value, used only when polling is done */;
-};
-
-/*
- * Init operations union
- */
-union init_op {
- struct init_raw_op raw /* raw init operation */;
- struct init_write_op write /* write init operation */;
- struct init_read_op read /* read init operation */;
- struct init_if_mode_op if_mode /* if_mode init operation */;
- struct init_if_phase_op if_phase /* if_phase init operation */;
- struct init_callback_op callback /* callback init operation */;
- struct init_delay_op delay /* delay init operation */;
-};
-
-/*
- * Init command operation types
- */
-enum init_op_types {
- INIT_OP_READ /* GRC read init command */,
- INIT_OP_WRITE /* GRC write init command */,
- INIT_OP_IF_MODE
- /* Skip init commands if the init modes expression doesn't match */,
- INIT_OP_IF_PHASE
- /* Skip init commands if the init phase doesn't match */,
- INIT_OP_DELAY /* delay init command */,
- INIT_OP_CALLBACK /* callback init command */,
- MAX_INIT_OP_TYPES
-};
-
-/*
- * init polling types
- */
-enum init_poll_types {
- INIT_POLL_NONE /* No polling */,
- INIT_POLL_EQ /* init value is included in the init command */,
- INIT_POLL_OR /* init value is all zeros */,
- INIT_POLL_AND /* init value is an array of values */,
- MAX_INIT_POLL_TYPES
-};
-
-/*
- * init source types
- */
-enum init_source_types {
- INIT_SRC_INLINE /* init value is included in the init command */,
- INIT_SRC_ZEROS /* init value is all zeros */,
- INIT_SRC_ARRAY /* init value is an array of values */,
- INIT_SRC_RUNTIME /* init value is provided during runtime */,
- MAX_INIT_SOURCE_TYPES
-};
-
-/*
- * Internal RAM Offsets macro data
- */
-struct iro {
- __le32 base /* RAM field offset */;
- __le16 m1 /* multiplier 1 */;
- __le16 m2 /* multiplier 2 */;
- __le16 m3 /* multiplier 3 */;
- __le16 size /* RAM field size */;
-};
-
-/*
- * register descriptor
- */
-struct reg_desc {
- __le32 data;
-#define REG_DESC_ADDRESS_MASK 0xFFFFFF
-#define REG_DESC_ADDRESS_SHIFT 0
-#define REG_DESC_SIZE_MASK 0xFF
-#define REG_DESC_SIZE_SHIFT 24
-};
-
-/*
- * Debug Bus block data
- */
-struct dbg_bus_block_data {
- u8 enabled /* Indicates if the block is enabled for recording (0/1) */;
- u8 hw_id /* HW ID associated with the block */;
- u8 line_num /* Debug line number to select */;
- u8 right_shift /* Number of units to right the debug data (0-3) */;
- u8 cycle_en /* 4-bit value: bit i set -> unit i is enabled. */;
- u8 force_valid /* 4-bit value: bit i set -> unit i is forced valid. */;
- u8 force_frame
- /* 4-bit value: bit i set -> unit i frame bit is forced. */;
- u8 reserved;
-};
-
-/*
- * Debug Bus Clients
- */
-enum dbg_bus_clients {
- DBG_BUS_CLIENT_RBCN,
- DBG_BUS_CLIENT_RBCP,
- DBG_BUS_CLIENT_RBCR,
- DBG_BUS_CLIENT_RBCT,
- DBG_BUS_CLIENT_RBCU,
- DBG_BUS_CLIENT_RBCF,
- DBG_BUS_CLIENT_RBCX,
- DBG_BUS_CLIENT_RBCS,
- DBG_BUS_CLIENT_RBCH,
- DBG_BUS_CLIENT_RBCZ,
- DBG_BUS_CLIENT_OTHER_ENGINE,
- DBG_BUS_CLIENT_TIMESTAMP,
- DBG_BUS_CLIENT_CPU,
- DBG_BUS_CLIENT_RBCY,
- DBG_BUS_CLIENT_RBCQ,
- DBG_BUS_CLIENT_RBCM,
- DBG_BUS_CLIENT_RBCB,
- DBG_BUS_CLIENT_RBCW,
- DBG_BUS_CLIENT_RBCV,
- MAX_DBG_BUS_CLIENTS
-};
-
-/*
- * Debug Bus constraint operation types
- */
-enum dbg_bus_constraint_ops {
- DBG_BUS_CONSTRAINT_OP_EQ /* equal */,
- DBG_BUS_CONSTRAINT_OP_NE /* not equal */,
- DBG_BUS_CONSTRAINT_OP_LT /* less than */,
- DBG_BUS_CONSTRAINT_OP_LTC /* less than (cyclic) */,
- DBG_BUS_CONSTRAINT_OP_LE /* less than or equal */,
- DBG_BUS_CONSTRAINT_OP_LEC /* less than or equal (cyclic) */,
- DBG_BUS_CONSTRAINT_OP_GT /* greater than */,
- DBG_BUS_CONSTRAINT_OP_GTC /* greater than (cyclic) */,
- DBG_BUS_CONSTRAINT_OP_GE /* greater than or equal */,
- DBG_BUS_CONSTRAINT_OP_GEC /* greater than or equal (cyclic) */,
- MAX_DBG_BUS_CONSTRAINT_OPS
-};
-
-/*
- * Debug Bus memory address
- */
-struct dbg_bus_mem_addr {
- __le32 lo;
- __le32 hi;
-};
-
-/*
- * Debug Bus PCI buffer data
- */
-struct dbg_bus_pci_buf_data {
- struct dbg_bus_mem_addr phys_addr /* PCI buffer physical address */;
- struct dbg_bus_mem_addr virt_addr /* PCI buffer virtual address */;
- __le32 size /* PCI buffer size in bytes */;
-};
-
-/*
- * Debug Bus Storm EID range filter params
- */
-struct dbg_bus_storm_eid_range_params {
- u8 min /* Minimal event ID to filter on */;
- u8 max /* Maximal event ID to filter on */;
-};
-
-/*
- * Debug Bus Storm EID mask filter params
- */
-struct dbg_bus_storm_eid_mask_params {
- u8 val /* Event ID value */;
- u8 mask /* Event ID mask. 1s in the mask = dont care bits. */;
-};
-
-/*
- * Debug Bus Storm EID filter params
- */
-union dbg_bus_storm_eid_params {
- struct dbg_bus_storm_eid_range_params range
- /* EID range filter params */;
- struct dbg_bus_storm_eid_mask_params mask /* EID mask filter params */;
-};
-
-/*
- * Debug Bus Storm data
- */
-struct dbg_bus_storm_data {
- u8 fast_enabled;
- u8 fast_mode
- /* Fast debug Storm mode, valid only if fast_enabled is set */;
- u8 slow_enabled;
- u8 slow_mode
- /* Slow debug Storm mode, valid only if slow_enabled is set */;
- u8 hw_id /* HW ID associated with the Storm */;
- u8 eid_filter_en /* Indicates if EID filtering is performed (0/1) */;
- u8 eid_range_not_mask;
- u8 cid_filter_en /* Indicates if CID filtering is performed (0/1) */;
- union dbg_bus_storm_eid_params eid_filter_params;
- __le16 reserved;
- __le32 cid /* CID to filter on. Valid only if cid_filter_en is set. */;
-};
-
-/*
- * Debug Bus data
- */
-struct dbg_bus_data {
- __le32 app_version /* The tools version number of the application */;
- u8 state /* The current debug bus state */;
- u8 hw_dwords /* HW dwords per cycle */;
- u8 next_hw_id /* Next HW ID to be associated with an input */;
- u8 num_enabled_blocks /* Number of blocks enabled for recording */;
- u8 num_enabled_storms /* Number of Storms enabled for recording */;
- u8 target /* Output target */;
- u8 next_trigger_state /* ID of next trigger state to be added */;
- u8 next_constraint_id
- /* ID of next filter/trigger constraint to be added */;
- u8 one_shot_en /* Indicates if one-shot mode is enabled (0/1) */;
- u8 grc_input_en /* Indicates if GRC recording is enabled (0/1) */;
- u8 timestamp_input_en
- /* Indicates if timestamp recording is enabled (0/1) */;
- u8 filter_en /* Indicates if the recording filter is enabled (0/1) */;
- u8 trigger_en /* Indicates if the recording trigger is enabled (0/1) */
- ;
- u8 adding_filter;
- u8 filter_pre_trigger;
- u8 filter_post_trigger;
- u8 unify_inputs;
- u8 rcv_from_other_engine;
- struct dbg_bus_pci_buf_data pci_buf;
- __le16 reserved;
- struct dbg_bus_block_data blocks[80] /* Debug Bus data for each block */
- ;
- struct dbg_bus_storm_data storms[6] /* Debug Bus data for each block */
- ;
-};
-
-/*
- * Debug bus filter types
- */
-enum dbg_bus_filter_types {
- DBG_BUS_FILTER_TYPE_OFF /* filter always off */,
- DBG_BUS_FILTER_TYPE_PRE /* filter before trigger only */,
- DBG_BUS_FILTER_TYPE_POST /* filter after trigger only */,
- DBG_BUS_FILTER_TYPE_ON /* filter always on */,
- MAX_DBG_BUS_FILTER_TYPES
-};
-
-/*
- * Debug bus frame modes
- */
-enum dbg_bus_frame_modes {
- DBG_BUS_FRAME_MODE_0HW_4ST = 0 /* 0 HW dwords, 4 Storm dwords */,
- DBG_BUS_FRAME_MODE_4HW_0ST = 3 /* 4 HW dwords, 0 Storm dwords */,
- DBG_BUS_FRAME_MODE_8HW_0ST = 4 /* 8 HW dwords, 0 Storm dwords */,
- MAX_DBG_BUS_FRAME_MODES
-};
-
-/*
- * Debug bus input types
- */
-enum dbg_bus_input_types {
- DBG_BUS_INPUT_TYPE_STORM,
- DBG_BUS_INPUT_TYPE_BLOCK,
- MAX_DBG_BUS_INPUT_TYPES
-};
-
-/*
- * Debug bus other engine mode
- */
-enum dbg_bus_other_engine_modes {
- DBG_BUS_OTHER_ENGINE_MODE_NONE,
- DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX,
- DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX,
- DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX,
- DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX,
- MAX_DBG_BUS_OTHER_ENGINE_MODES
-};
-
-/*
- * Debug bus post-trigger recording types
- */
-enum dbg_bus_post_trigger_types {
- DBG_BUS_POST_TRIGGER_RECORD /* start recording after trigger */,
- DBG_BUS_POST_TRIGGER_DROP /* drop data after trigger */,
- MAX_DBG_BUS_POST_TRIGGER_TYPES
-};
-
-/*
- * Debug bus pre-trigger recording types
- */
-enum dbg_bus_pre_trigger_types {
- DBG_BUS_PRE_TRIGGER_START_FROM_ZERO /* start recording from time 0 */,
- DBG_BUS_PRE_TRIGGER_NUM_CHUNKS
- /* start recording some chunks before trigger */,
- DBG_BUS_PRE_TRIGGER_DROP /* drop data before trigger */,
- MAX_DBG_BUS_PRE_TRIGGER_TYPES
-};
-
-/*
- * Debug bus SEMI frame modes
- */
-enum dbg_bus_semi_frame_modes {
- DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST =
- 0 /* 0 slow dwords, 4 fast dwords */,
- DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST =
- 3 /* 4 slow dwords, 0 fast dwords */,
- MAX_DBG_BUS_SEMI_FRAME_MODES
-};
-
-/*
- * Debug bus states
- */
-enum dbg_bus_states {
- DBG_BUS_STATE_BEFORE_RECORD /* before debug bus the recording starts */
- ,
- DBG_BUS_STATE_DURING_RECORD /* during debug bus recording */,
- DBG_BUS_STATE_AFTER_RECORD /* after debug bus recording */,
- MAX_DBG_BUS_STATES
-};
-
-/*
- * Debug Bus Storm modes
- */
-enum dbg_bus_storm_modes {
- DBG_BUS_STORM_MODE_PRINTF /* store data (fast debug) */,
- DBG_BUS_STORM_MODE_PRAM_ADDR /* pram address (fast debug) */,
- DBG_BUS_STORM_MODE_DRA_RW /* DRA read/write data (fast debug) */,
- DBG_BUS_STORM_MODE_DRA_W /* DRA write data (fast debug) */,
- DBG_BUS_STORM_MODE_LD_ST_ADDR /* load/store address (fast debug) */,
- DBG_BUS_STORM_MODE_DRA_FSM /* DRA state machines (fast debug) */,
- DBG_BUS_STORM_MODE_RH /* recording handlers (fast debug) */,
- DBG_BUS_STORM_MODE_FOC /* FOC: FIN + DRA Rd (slow debug) */,
- DBG_BUS_STORM_MODE_EXT_STORE /* FOC: External Store (slow) */,
- MAX_DBG_BUS_STORM_MODES
-};
-
-/*
- * Debug bus target IDs
- */
-enum dbg_bus_targets {
- DBG_BUS_TARGET_ID_INT_BUF
- /* records debug bus to DBG block internal buffer */,
- DBG_BUS_TARGET_ID_NIG /* records debug bus to the NW */,
- DBG_BUS_TARGET_ID_PCI /* records debug bus to a PCI buffer */,
- MAX_DBG_BUS_TARGETS
-};
-
-/*
- * GRC Dump data
- */
-struct dbg_grc_data {
- u8 is_updated /* Indicates if the GRC Dump data is updated (0/1) */;
- u8 chip_id /* Chip ID */;
- u8 chip_mask /* Chip mask */;
- u8 reserved;
- __le32 max_dump_dwords /* Max GRC Dump size in dwords */;
- __le32 param_val[40];
- u8 param_set_by_user[40];
-};
-
-/*
- * Debug GRC params
- */
-enum dbg_grc_params {
- DBG_GRC_PARAM_DUMP_TSTORM /* dump Tstorm memories (0/1) */,
- DBG_GRC_PARAM_DUMP_MSTORM /* dump Mstorm memories (0/1) */,
- DBG_GRC_PARAM_DUMP_USTORM /* dump Ustorm memories (0/1) */,
- DBG_GRC_PARAM_DUMP_XSTORM /* dump Xstorm memories (0/1) */,
- DBG_GRC_PARAM_DUMP_YSTORM /* dump Ystorm memories (0/1) */,
- DBG_GRC_PARAM_DUMP_PSTORM /* dump Pstorm memories (0/1) */,
- DBG_GRC_PARAM_DUMP_REGS /* dump non-memory registers (0/1) */,
- DBG_GRC_PARAM_DUMP_RAM /* dump Storm internal RAMs (0/1) */,
- DBG_GRC_PARAM_DUMP_PBUF /* dump Storm passive buffer (0/1) */,
- DBG_GRC_PARAM_DUMP_IOR /* dump Storm IORs (0/1) */,
- DBG_GRC_PARAM_DUMP_VFC /* dump VFC memories (0/1) */,
- DBG_GRC_PARAM_DUMP_CM_CTX /* dump CM contexts (0/1) */,
- DBG_GRC_PARAM_DUMP_PXP /* dump PXP memories (0/1) */,
- DBG_GRC_PARAM_DUMP_RSS /* dump RSS memories (0/1) */,
- DBG_GRC_PARAM_DUMP_CAU /* dump CAU memories (0/1) */,
- DBG_GRC_PARAM_DUMP_QM /* dump QM memories (0/1) */,
- DBG_GRC_PARAM_DUMP_MCP /* dump MCP memories (0/1) */,
- DBG_GRC_PARAM_RESERVED /* reserved */,
- DBG_GRC_PARAM_DUMP_CFC /* dump CFC memories (0/1) */,
- DBG_GRC_PARAM_DUMP_IGU /* dump IGU memories (0/1) */,
- DBG_GRC_PARAM_DUMP_BRB /* dump BRB memories (0/1) */,
- DBG_GRC_PARAM_DUMP_BTB /* dump BTB memories (0/1) */,
- DBG_GRC_PARAM_DUMP_BMB /* dump BMB memories (0/1) */,
- DBG_GRC_PARAM_DUMP_NIG /* dump NIG memories (0/1) */,
- DBG_GRC_PARAM_DUMP_MULD /* dump MULD memories (0/1) */,
- DBG_GRC_PARAM_DUMP_PRS /* dump PRS memories (0/1) */,
- DBG_GRC_PARAM_DUMP_DMAE /* dump PRS memories (0/1) */,
- DBG_GRC_PARAM_DUMP_TM /* dump TM (timers) memories (0/1) */,
- DBG_GRC_PARAM_DUMP_SDM /* dump SDM memories (0/1) */,
- DBG_GRC_PARAM_DUMP_STATIC /* dump static debug data (0/1) */,
- DBG_GRC_PARAM_UNSTALL /* un-stall Storms after dump (0/1) */,
- DBG_GRC_PARAM_NUM_LCIDS /* number of LCIDs (0..320) */,
- DBG_GRC_PARAM_NUM_LTIDS /* number of LTIDs (0..320) */,
- DBG_GRC_PARAM_EXCLUDE_ALL
- /* preset: exclude all memories from dump (1 only) */,
- DBG_GRC_PARAM_CRASH
- /* preset: include memories for crash dump (1 only) */,
- DBG_GRC_PARAM_PARITY_SAFE
- /* perform dump only if MFW is responding (0/1) */,
- DBG_GRC_PARAM_DUMP_CM /* dump CM memories (0/1) */,
- MAX_DBG_GRC_PARAMS
-};
-
-/*
- * Debug reset registers
- */
-enum dbg_reset_regs {
- DBG_RESET_REG_MISCS_PL_UA,
- DBG_RESET_REG_MISCS_PL_HV,
- DBG_RESET_REG_MISC_PL_UA,
- DBG_RESET_REG_MISC_PL_HV,
- DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
- DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
- DBG_RESET_REG_MISC_PL_PDA_VAUX,
- MAX_DBG_RESET_REGS
-};
-
-/*
- * @DPDK Debug status codes
- */
-enum dbg_status {
- DBG_STATUS_OK,
- DBG_STATUS_APP_VERSION_NOT_SET,
- DBG_STATUS_UNSUPPORTED_APP_VERSION,
- DBG_STATUS_DBG_BLOCK_NOT_RESET,
- DBG_STATUS_INVALID_ARGS,
- DBG_STATUS_OUTPUT_ALREADY_SET,
- DBG_STATUS_INVALID_PCI_BUF_SIZE,
- DBG_STATUS_PCI_BUF_ALLOC_FAILED,
- DBG_STATUS_PCI_BUF_NOT_ALLOCATED,
- DBG_STATUS_TOO_MANY_INPUTS,
- DBG_STATUS_INPUT_OVERLAP,
- DBG_STATUS_HW_ONLY_RECORDING,
- DBG_STATUS_STORM_ALREADY_ENABLED,
- DBG_STATUS_STORM_NOT_ENABLED,
- DBG_STATUS_BLOCK_ALREADY_ENABLED,
- DBG_STATUS_BLOCK_NOT_ENABLED,
- DBG_STATUS_NO_INPUT_ENABLED,
- DBG_STATUS_NO_FILTER_TRIGGER_64B,
- DBG_STATUS_FILTER_ALREADY_ENABLED,
- DBG_STATUS_TRIGGER_ALREADY_ENABLED,
- DBG_STATUS_TRIGGER_NOT_ENABLED,
- DBG_STATUS_CANT_ADD_CONSTRAINT,
- DBG_STATUS_TOO_MANY_TRIGGER_STATES,
- DBG_STATUS_TOO_MANY_CONSTRAINTS,
- DBG_STATUS_RECORDING_NOT_STARTED,
- DBG_STATUS_NO_DATA_TRIGGERED,
- DBG_STATUS_NO_DATA_RECORDED,
- DBG_STATUS_DUMP_BUF_TOO_SMALL,
- DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED,
- DBG_STATUS_UNKNOWN_CHIP,
- DBG_STATUS_VIRT_MEM_ALLOC_FAILED,
- DBG_STATUS_BLOCK_IN_RESET,
- DBG_STATUS_INVALID_TRACE_SIGNATURE,
- DBG_STATUS_INVALID_NVRAM_BUNDLE,
- DBG_STATUS_NVRAM_GET_IMAGE_FAILED,
- DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE,
- DBG_STATUS_NVRAM_READ_FAILED,
- DBG_STATUS_IDLE_CHK_PARSE_FAILED,
- DBG_STATUS_MCP_TRACE_BAD_DATA,
- DBG_STATUS_MCP_TRACE_NO_META,
- DBG_STATUS_MCP_COULD_NOT_HALT,
- DBG_STATUS_MCP_COULD_NOT_RESUME,
- DBG_STATUS_DMAE_FAILED,
- DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
- DBG_STATUS_IGU_FIFO_BAD_DATA,
- DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
- DBG_STATUS_FW_ASSERTS_PARSE_FAILED,
- DBG_STATUS_REG_FIFO_BAD_DATA,
- DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
- MAX_DBG_STATUS
-};
-
-/*
- * Debug Storms IDs
- */
-enum dbg_storms {
- DBG_TSTORM_ID,
- DBG_MSTORM_ID,
- DBG_USTORM_ID,
- DBG_XSTORM_ID,
- DBG_YSTORM_ID,
- DBG_PSTORM_ID,
- MAX_DBG_STORMS
-};
-
-/*
- * Idle Check data
- */
-struct idle_chk_data {
- __le32 buf_size /* Idle check buffer size in dwords */;
- u8 buf_size_set
- /* Indicates if the idle check buffer size was set (0/1) */;
- u8 reserved1;
- __le16 reserved2;
-};
-
-/*
- * Idle Check data
- */
-struct mcp_trace_data {
- __le32 buf_size /* MCP Trace buffer size in dwords */;
- u8 buf_size_set
- /* Indicates if the MCP Trace buffer size was set (0/1) */;
- u8 reserved1;
- __le16 reserved2;
-};
-
-/*
- * Debug Tools data (per HW function)
- */
-struct dbg_tools_data {
- struct dbg_grc_data grc /* GRC Dump data */;
- struct dbg_bus_data bus /* Debug Bus data */;
- struct idle_chk_data idle_chk /* Idle Check data */;
- struct mcp_trace_data mcp_trace /* MCP Trace data */;
- u8 block_in_reset[80] /* Indicates if a block is in reset state (0/1) */
- ;
- u8 chip_id /* Chip ID (from enum chip_ids) */;
- u8 chip_mask
- /* Chip mask = bit index chip_id is set, the rest are cleared */;
- u8 initialized /* Indicates if the data was initialized */;
- u8 reset_state_updated
- /* Indicates if blocks reset state is updated (0/1) */;
-};
-
-/*
- * BRB RAM init requirements
- */
-struct init_brb_ram_req {
- __le32 guranteed_per_tc /* guaranteed size per TC, in bytes */;
- __le32 headroom_per_tc /* headroom size per TC, in bytes */;
- __le32 min_pkt_size /* min packet size, in bytes */;
- __le32 max_ports_per_engine /* min packet size, in bytes */;
- u8 num_active_tcs[MAX_NUM_PORTS] /* number of active TCs per port */;
-};
-
-/*
- * ETS per-TC init requirements
- */
-struct init_ets_tc_req {
- u8 use_sp;
- u8 use_wfq;
- __le16 weight /* An arbitration weight. Valid only if use_wfq is set. */
- ;
-};
-
-/*
- * ETS init requirements
- */
-struct init_ets_req {
- __le32 mtu /* Max packet size (in bytes) */;
- struct init_ets_tc_req tc_req[NUM_OF_TCS]
- /* ETS initialization requirements per TC. */;
-};
-
-/*
- * NIG LB RL init requirements
- */
-struct init_nig_lb_rl_req {
- __le16 lb_mac_rate;
- __le16 lb_rate;
- __le32 mtu /* Max packet size (in bytes) */;
- __le16 tc_rate[NUM_OF_PHYS_TCS];
-};
-
-/*
- * NIG TC mapping for each priority
- */
-struct init_nig_pri_tc_map_entry {
- u8 tc_id /* the mapped TC ID */;
- u8 valid /* indicates if the mapping entry is valid */;
-};
-
-/*
- * NIG priority to TC map init requirements
- */
-struct init_nig_pri_tc_map_req {
- struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
-};
-
-/*
- * QM per-port init parameters
- */
-struct init_qm_port_params {
- u8 active /* Indicates if this port is active */;
- u8 num_active_phys_tcs /* number of physical TCs used by this port */;
- __le16 num_pbf_cmd_lines
- /* number of PBF command lines that can be used by this port */;
- __le16 num_btb_blocks
- /* number of BTB blocks that can be used by this port */;
- __le16 reserved;
-};
-
-/*
- * QM per-PQ init parameters
- */
-struct init_qm_pq_params {
- u8 vport_id /* VPORT ID */;
- u8 tc_id /* TC ID */;
- u8 wrr_group /* WRR group */;
- u8 reserved;
-};
-
-/*
- * QM per-vport init parameters
- */
-struct init_qm_vport_params {
- __le32 vport_rl;
- __le16 vport_wfq;
- __le16 first_tx_pq_id[NUM_OF_TCS]
- /* the first Tx PQ ID associated with this VPORT for each TC. */;
-};
-
-#endif /* __ECORE_HSI_TOOLS__ */
#include "reg_addr.h"
#include "ecore_rt_defs.h"
#include "ecore_hsi_common.h"
-#include "ecore_hsi_tools.h"
+#include "ecore_hsi_init_func.h"
+#include "ecore_hsi_init_tool.h"
#include "ecore_init_fw_funcs.h"
/* @DPDK CmInterfaceEnum */
struct init_qm_port_params
port_params[MAX_NUM_PORTS])
{
- u8 tc, voq, port_id;
+ u8 tc, voq, port_id, num_tcs_in_port;
bool eagle_workaround = ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn);
/* clear PBF lines for all VOQs */
for (voq = 0; voq < MAX_NUM_VOQS; voq++)
if (eagle_workaround)
phys_lines -= PBF_CMDQ_EAGLE_WORKAROUND_LINES;
/* find #lines per active physical TC */
- phys_lines_per_tc =
- phys_lines /
- port_params[port_id].num_active_phys_tcs;
+ num_tcs_in_port = 0;
+ for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
+ if (((port_params[port_id].active_phys_tcs >>
+ tc) & 0x1) == 1)
+ num_tcs_in_port++;
+ }
+ phys_lines_per_tc = phys_lines / num_tcs_in_port;
/* init registers per active TC */
- for (tc = 0;
- tc < port_params[port_id].num_active_phys_tcs;
- tc++) {
- voq =
- PHYS_VOQ(port_id, tc,
- max_phys_tcs_per_port);
- ecore_cmdq_lines_voq_rt_init(p_hwfn, voq,
- phys_lines_per_tc);
+ for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
+ if (((port_params[port_id].active_phys_tcs >>
+ tc) & 0x1) == 1) {
+ voq = PHYS_VOQ(port_id, tc,
+ max_phys_tcs_per_port);
+ ecore_cmdq_lines_voq_rt_init(p_hwfn,
+ voq, phys_lines_per_tc);
+ }
}
/* init registers for pure LB TC */
ecore_cmdq_lines_voq_rt_init(p_hwfn, LB_VOQ(port_id),
struct init_qm_port_params
port_params[MAX_NUM_PORTS])
{
- u8 tc, voq, port_id;
+ u8 tc, voq, port_id, num_tcs_in_port;
u32 usable_blocks, pure_lb_blocks, phys_blocks;
bool eagle_workaround = ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn);
for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
BTB_HEADROOM_BLOCKS;
if (eagle_workaround)
usable_blocks -= BTB_EAGLE_WORKAROUND_BLOCKS;
+
+ num_tcs_in_port = 0;
+ for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++)
+ if (((port_params[port_id].active_phys_tcs >>
+ tc) & 0x1) == 1)
+ num_tcs_in_port++;
pure_lb_blocks =
(usable_blocks * BTB_PURE_LB_FACTOR) /
- (port_params[port_id].num_active_phys_tcs *
+ (num_tcs_in_port *
BTB_PURE_LB_FACTOR + BTB_PURE_LB_RATIO);
pure_lb_blocks =
OSAL_MAX_T(u32, BTB_JUMBO_PKT_BLOCKS,
phys_blocks =
(usable_blocks -
pure_lb_blocks) /
- port_params[port_id].num_active_phys_tcs;
+ num_tcs_in_port;
/* init physical TCs */
for (tc = 0;
- tc < port_params[port_id].num_active_phys_tcs;
+ tc < NUM_OF_PHYS_TCS;
tc++) {
- voq =
- PHYS_VOQ(port_id, tc,
- max_phys_tcs_per_port);
- STORE_RT_REG(p_hwfn,
+ if (((port_params[port_id].active_phys_tcs >>
+ tc) & 0x1) == 1) {
+ voq = PHYS_VOQ(port_id, tc,
+ max_phys_tcs_per_port);
+ STORE_RT_REG(p_hwfn,
PBF_BTB_GUARANTEED_RT_OFFSET(voq),
phys_blocks);
+ }
}
/* init pure LB TC */
STORE_RT_REG(p_hwfn,
(QM_OPPOR_PQ_EMPTY_DEF <<
QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT);
STORE_RT_REG(p_hwfn, QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET, mask);
- /* check eagle workaround */
- for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
- if (port_params[port_id].active &&
- port_params[port_id].num_active_phys_tcs >
- EAGLE_WORKAROUND_TC &&
- ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn)) {
- DP_NOTICE(p_hwfn, true,
- "Can't config 8 TCs with Eagle"
- " eng1 workaround");
- return -1;
- }
- }
/* enable/disable PF RL */
ecore_enable_pf_rl(p_hwfn, pf_rl_en);
/* enable/disable PF WFQ */
buf_hdr = (struct bin_buffer_hdr *)(uintptr_t)data;
- offset = buf_hdr[BIN_BUF_FW_VER_INFO].offset;
+ offset = buf_hdr[BIN_BUF_INIT_FW_VER_INFO].offset;
fw->fw_ver_info = (struct fw_ver_info *)((uintptr_t)(data + offset));
offset = buf_hdr[BIN_BUF_INIT_CMD].offset;
#define ECORE_PGLUE_ATTENTION_ILT_VALID (1 << 23)
static enum _ecore_status_t ecore_pglub_rbc_attn_cb(struct ecore_hwfn *p_hwfn)
{
- u32 tmp, reg_addr;
-
- reg_addr =
- attn_blocks[BLOCK_PGLUE_B].chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].
- int_regs[0]->mask_addr;
-
- /* Mask unnecessary attentions -@TBD move to MFW */
- tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, reg_addr);
- tmp |= (1 << 19); /* Was PGL_PCIE_ATTN */
- ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, reg_addr, tmp);
+ u32 tmp;
tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
PGLUE_B_REG_TX_ERR_WR_DETAILS2);
return ECORE_SUCCESS;
}
-static enum _ecore_status_t ecore_nig_attn_cb(struct ecore_hwfn *p_hwfn)
-{
- u32 tmp, reg_addr;
-
- /* Mask unnecessary attentions -@TBD move to MFW */
- reg_addr =
- attn_blocks[BLOCK_NIG].chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].
- int_regs[3]->mask_addr;
- tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, reg_addr);
- tmp |= (1 << 0); /* Was 3_P0_TX_PAUSE_TOO_LONG_INT */
- tmp |= NIG_REG_INT_MASK_3_P0_LB_TC1_PAUSE_TOO_LONG_INT;
- ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, reg_addr, tmp);
-
- reg_addr =
- attn_blocks[BLOCK_NIG].chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].
- int_regs[5]->mask_addr;
- tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, reg_addr);
- tmp |= (1 << 0); /* Was 5_P1_TX_PAUSE_TOO_LONG_INT */
- ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, reg_addr, tmp);
-
- /* TODO - a bit risky to return success here; But alternative is to
- * actually read the multitdue of interrupt register of the block.
- */
- return ECORE_SUCCESS;
-}
-
static enum _ecore_status_t ecore_fw_assertion(struct ecore_hwfn *p_hwfn)
{
DP_NOTICE(p_hwfn, false, "FW assertion!\n");
{"MSTAT per-path", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
{"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
MAX_BLOCK_ID},
- {"NIG", ATTENTION_PAR_INT, ecore_nig_attn_cb, BLOCK_NIG},
+ {"NIG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NIG},
{"BMB/OPTE/MCP", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BMB},
{"BTB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BTB},
{"BRB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BRB},
rc = p_aeu->cb(p_hwfn);
}
- /* Handle HW block interrupt registers */
- if (p_aeu->block_index != MAX_BLOCK_ID) {
- u16 chip_type = ECORE_GET_TYPE(p_hwfn->p_dev);
- struct attn_hw_block *p_block;
- int i;
-
- p_block = &attn_blocks[p_aeu->block_index];
-
- /* Handle each interrupt register */
- for (i = 0;
- i < p_block->chip_regs[chip_type].num_of_int_regs; i++) {
- struct attn_hw_reg *p_reg_desc;
- u32 sts_addr;
-
- p_reg_desc = p_block->chip_regs[chip_type].int_regs[i];
-
- /* In case of fatal attention, don't clear the status
- * so it would appear in idle check.
- */
- if (rc == ECORE_SUCCESS)
- sts_addr = p_reg_desc->sts_clr_addr;
- else
- sts_addr = p_reg_desc->sts_addr;
-
- val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, sts_addr);
- mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
- p_reg_desc->mask_addr);
- ecore_int_deassertion_print_bit(p_hwfn, p_reg_desc,
- p_block,
- ECORE_ATTN_TYPE_ATTN,
- val, mask);
-
-#ifndef REMOVE_DBG
- interrupts[i] = val;
-#endif
- }
- }
+ /* Print HW block interrupt registers */
+ if (p_aeu->block_index != MAX_BLOCK_ID)
+ DP_NOTICE(p_hwfn->p_dev, false, "[block_id %d type %d]\n",
+ p_aeu->block_index, ATTN_TYPE_INTERRUPT);
/* Reach assertion if attention is fatal */
if (rc != ECORE_SUCCESS) {
return rc;
}
-static void ecore_int_parity_print(struct ecore_hwfn *p_hwfn,
- struct aeu_invert_reg_bit *p_aeu,
- struct attn_hw_block *p_block, u8 bit_index)
-{
- u16 chip_type = ECORE_GET_TYPE(p_hwfn->p_dev);
- int i;
-
- for (i = 0; i < p_block->chip_regs[chip_type].num_of_prty_regs; i++) {
- struct attn_hw_reg *p_reg_desc;
- u32 val, mask;
-
- p_reg_desc = p_block->chip_regs[chip_type].prty_regs[i];
-
- val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
- p_reg_desc->sts_clr_addr);
- mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
- p_reg_desc->mask_addr);
- DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
- "%s[%d] - parity register[%d] is %08x [mask is %08x]\n",
- p_aeu->bit_name, bit_index, i, val, mask);
- ecore_int_deassertion_print_bit(p_hwfn, p_reg_desc,
- p_block,
- ECORE_ATTN_TYPE_PARITY,
- val, mask);
- }
-}
-
/**
* @brief ecore_int_deassertion_parity - handle a single parity AEU source
*
DP_INFO(p_hwfn->p_dev, "%s[%d] parity attention is set\n",
p_aeu->bit_name, bit_index);
- if (block_id != MAX_BLOCK_ID) {
- ecore_int_parity_print(p_hwfn, p_aeu, &attn_blocks[block_id],
- bit_index);
-
- /* In A0, there's a single parity bit for several blocks */
- if (block_id == BLOCK_BTB) {
- ecore_int_parity_print(p_hwfn, p_aeu,
- &attn_blocks[BLOCK_OPTE],
- bit_index);
- ecore_int_parity_print(p_hwfn, p_aeu,
- &attn_blocks[BLOCK_MCP],
- bit_index);
- }
+ if (block_id != MAX_BLOCK_ID)
+ return;
+
+ /* In A0, there's a single parity bit for several blocks */
+ if (block_id == BLOCK_BTB) {
+ DP_NOTICE(p_hwfn->p_dev, false, "[block_id %d type %d]\n",
+ BLOCK_OPTE, ATTN_TYPE_PARITY);
+ DP_NOTICE(p_hwfn->p_dev, false, "[block_id %d type %d]\n",
+ BLOCK_MCP, ATTN_TYPE_PARITY);
}
}
enum ecore_int_mode int_mode)
{
enum _ecore_status_t rc = ECORE_SUCCESS;
- u32 tmp, reg_addr;
+ u32 tmp;
/* @@@tmp - Mask General HW attentions 0-31, Enable 32-36 */
tmp = ecore_rd(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0);
tmp &= ~0x800;
ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0, tmp);
- /* @@@tmp - Mask interrupt sources - should move to init tool;
- * Also, correct for A0 [might still change in B0.
- */
- reg_addr =
- attn_blocks[BLOCK_BRB].chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].
- int_regs[0]->mask_addr;
- tmp = ecore_rd(p_hwfn, p_ptt, reg_addr);
- tmp |= (1 << 21); /* Was PKT4_LEN_ERROR */
- ecore_wr(p_hwfn, p_ptt, reg_addr, tmp);
-
ecore_int_igu_enable_attn(p_hwfn, p_ptt);
if ((int_mode != ECORE_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {
git.droids-corp.org / dpdk.git / commitdiff