uint32_t max_mcast_addr; /* maximum number of mcast filters supported */
struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
+ uint16_t tunnel_disable_flag; /* tunnel stateless offloads status */
};
static
bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT;
PMD_DRV_LOG(DEBUG, "VLAN acceleration for TX is enabled\n");
}
+
+ bp->tunnel_disable_flag = rte_le_to_cpu_16(resp->tunnel_disable_flag);
+ if (bp->tunnel_disable_flag)
+ PMD_DRV_LOG(DEBUG, "Tunnel parsing capability is disabled, flags : %#x\n",
+ bp->tunnel_disable_flag);
unlock:
HWRM_UNLOCK();
#define BNXT_CTX_VAL_INVAL 0xFFFF
+#define BNXT_TUNNELED_OFFLOADS_CAP_VXLAN_EN(bp) \
+ (!((bp)->tunnel_disable_flag & HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN))
+#define BNXT_TUNNELED_OFFLOADS_CAP_NGE_EN(bp) \
+ (!((bp)->tunnel_disable_flag & HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_NGE))
+#define BNXT_TUNNELED_OFFLOADS_CAP_GRE_EN(bp) \
+ (!((bp)->tunnel_disable_flag & HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_GRE))
+#define BNXT_TUNNELED_OFFLOADS_CAP_IPINIP_EN(bp) \
+ (!((bp)->tunnel_disable_flag & HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP))
+
+/*
+ * If the device supports VXLAN, GRE, IPIP and GENEVE tunnel parsing, then report
+ * RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM and
+ * RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM in the Rx/Tx offload capabilities of the device.
+ */
+#define BNXT_TUNNELED_OFFLOADS_CAP_ALL_EN(bp) \
+ (BNXT_TUNNELED_OFFLOADS_CAP_VXLAN_EN(bp) && \
+ BNXT_TUNNELED_OFFLOADS_CAP_NGE_EN(bp) && \
+ BNXT_TUNNELED_OFFLOADS_CAP_GRE_EN(bp) && \
+ BNXT_TUNNELED_OFFLOADS_CAP_IPINIP_EN(bp))
+
int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp,
struct bnxt_vnic_info *vnic);
int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic,
RTE_ETH_RX_OFFLOAD_SCATTER |
RTE_ETH_RX_OFFLOAD_RSS_HASH;
- rx_offload_capa |= RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
- RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM;
-
if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TIMESTAMP;
if (bp->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP)
rx_offload_capa |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
+ if (BNXT_TUNNELED_OFFLOADS_CAP_ALL_EN(bp))
+ rx_offload_capa |= RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
+ RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM;
+
return rx_offload_capa;
}
RTE_ETH_TX_OFFLOAD_QINQ_INSERT |
RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
- tx_offload_capa |= RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
- RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
- RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO |
- RTE_ETH_TX_OFFLOAD_IPIP_TNL_TSO |
- RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO;
-
if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT)
tx_offload_capa |= RTE_ETH_TX_OFFLOAD_VLAN_INSERT;
+ if (BNXT_TUNNELED_OFFLOADS_CAP_ALL_EN(bp))
+ tx_offload_capa |= RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM;
+
+ if (BNXT_TUNNELED_OFFLOADS_CAP_VXLAN_EN(bp))
+ tx_offload_capa |= RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO;
+ if (BNXT_TUNNELED_OFFLOADS_CAP_GRE_EN(bp))
+ tx_offload_capa |= RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO;
+ if (BNXT_TUNNELED_OFFLOADS_CAP_NGE_EN(bp))
+ tx_offload_capa |= RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO;
+ if (BNXT_TUNNELED_OFFLOADS_CAP_IPINIP_EN(bp))
+ tx_offload_capa |= RTE_ETH_TX_OFFLOAD_IPIP_TNL_TSO;
+
return tx_offload_capa;
}