Add new API to get the board info.
opae_mgr_get_board_info()
Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
Signed-off-by: Andy Pei <andy.pei@intel.com>
return fme_mgr_get_sensor_value(fme, sensor, value);
}
+static int ifpga_mgr_get_board_info(struct opae_manager *mgr,
+ struct opae_board_info **info)
+{
+ struct ifpga_fme_hw *fme = mgr->data;
+
+ *info = &fme->board_info;
+
+ return 0;
+}
+
struct opae_manager_ops ifpga_mgr_ops = {
.flash = ifpga_mgr_flash,
.get_eth_group_region_info = ifpga_mgr_get_eth_group_region_info,
.get_sensor_value = ifpga_mgr_get_sensor_value,
+ .get_board_info = ifpga_mgr_get_board_info,
};
static int ifpga_mgr_read_mac_rom(struct opae_manager *mgr, int offset,
(((bts_hdr)->guid_h == GBS_GUID_H) && \
((bts_hdr)->guid_l == GBS_GUID_L))
+#define check_support(n) (n == 1 ? "support" : "no")
+
/* bitstream id definition */
struct fme_bitstream_id {
union {
u64 id;
struct {
- u64 hash:32;
- u64 interface:4;
- u64 reserved:12;
- u64 debug:4;
- u64 patch:4;
- u64 minor:4;
- u64 major:4;
+ u8 build_patch:8;
+ u8 build_minor:8;
+ u8 build_major:8;
+ u8 fvl_bypass:1;
+ u8 mac_lightweight:1;
+ u8 disagregate:1;
+ u8 lightweiht:1;
+ u8 seu:1;
+ u8 ptp:1;
+ u8 reserve:2;
+ u8 interface:4;
+ u32 afu_revision:12;
+ u8 patch:4;
+ u8 minor:4;
+ u8 major:4;
+ u8 reserved:4;
};
};
};
VC_2_2_25G = 4,
};
-struct ifpga_fme_board_info {
+enum pac_major {
+ VISTA_CREEK = 0,
+ RUSH_CREEK = 1,
+ DARBY_CREEK = 2,
+};
+
+enum pac_minor {
+ DCP_1_0 = 0,
+ DCP_1_1 = 1,
+ DCP_1_2 = 2,
+};
+
+struct opae_board_info {
+ enum pac_major major;
+ enum pac_minor minor;
enum board_interface type;
- u32 build_hash;
- u32 debug_version;
- u32 patch_version;
- u32 minor_version;
- u32 major_version;
+
+ /* PAC features */
+ u8 fvl_bypass;
+ u8 mac_lightweight;
+ u8 disaggregate;
+ u8 lightweight;
+ u8 seu;
+ u8 ptp;
+
u32 max10_version;
u32 nios_fw_version;
u32 nums_of_retimer;
return "unknown";
}
+static const char *board_major_to_string(u32 major)
+{
+ switch (major) {
+ case VISTA_CREEK:
+ return "VISTA_CREEK";
+ case RUSH_CREEK:
+ return "RUSH_CREEK";
+ case DARBY_CREEK:
+ return "DARBY_CREEK";
+ }
+
+ return "unknown";
+}
+
static int board_type_to_info(u32 type,
- struct ifpga_fme_board_info *info)
+ struct opae_board_info *info)
{
switch (type) {
case VC_8_10G:
if (fme_hdr_get_bitstream_id(fme, &id.id))
return -EINVAL;
+ fme->board_info.major = id.major;
+ fme->board_info.minor = id.minor;
fme->board_info.type = id.interface;
- fme->board_info.build_hash = id.hash;
- fme->board_info.debug_version = id.debug;
- fme->board_info.major_version = id.major;
- fme->board_info.minor_version = id.minor;
-
- dev_info(fme, "board type: %s major_version:%u minor_version:%u build_hash:%u\n",
- board_type_to_string(fme->board_info.type),
- fme->board_info.major_version,
- fme->board_info.minor_version,
- fme->board_info.build_hash);
+ fme->board_info.fvl_bypass = id.fvl_bypass;
+ fme->board_info.mac_lightweight = id.mac_lightweight;
+ fme->board_info.lightweight = id.lightweiht;
+ fme->board_info.disaggregate = id.disagregate;
+ fme->board_info.seu = id.seu;
+ fme->board_info.ptp = id.ptp;
+
+ dev_info(fme, "found: board: %s type: %s\n",
+ board_major_to_string(fme->board_info.major),
+ board_type_to_string(fme->board_info.type));
+
+ dev_info(fme, "support feature:\n"
+ "fvl_bypass:%s\n"
+ "mac_lightweight:%s\n"
+ "lightweight:%s\n"
+ "disaggregate:%s\n"
+ "seu:%s\n"
+ "ptp1588:%s\n",
+ check_support(fme->board_info.fvl_bypass),
+ check_support(fme->board_info.mac_lightweight),
+ check_support(fme->board_info.lightweight),
+ check_support(fme->board_info.disaggregate),
+ check_support(fme->board_info.seu),
+ check_support(fme->board_info.ptp));
+
if (board_type_to_info(fme->board_info.type, &fme->board_info))
return -EINVAL;
void *eth_dev[MAX_ETH_GROUP_DEVICES];
struct opae_reg_region
eth_group_region[MAX_ETH_GROUP_DEVICES];
- struct ifpga_fme_board_info board_info;
+ struct opae_board_info board_info;
int nums_eth_dev;
unsigned int nums_acc_region;
};
return -ENOENT;
}
+
+/**
+ * opae_manager_get_board_info - get board info
+ * sensor value
+ * @info: opae_board_info for the card
+ *
+ * Return: 0 on success, otherwise error code
+ */
+int
+opae_mgr_get_board_info(struct opae_manager *mgr,
+ struct opae_board_info **info)
+{
+ if (!mgr || !info)
+ return -EINVAL;
+
+ if (mgr->ops && mgr->ops->get_board_info)
+ return mgr->ops->get_board_info(mgr, info);
+
+ return -ENOENT;
+}
#include "opae_osdep.h"
#include "opae_intel_max10.h"
#include "opae_eth_group.h"
+#include "ifpga_defines.h"
#ifndef PCI_MAX_RESOURCE
#define PCI_MAX_RESOURCE 6
int (*get_sensor_value)(struct opae_manager *mgr,
struct opae_sensor_info *sensor,
unsigned int *value);
+ int (*get_board_info)(struct opae_manager *mgr,
+ struct opae_board_info **info);
};
/* networking management ops in FME */
u8 type, u8 index, u16 addr, u32 data);
int opae_manager_eth_group_read_reg(struct opae_manager *mgr, u8 group_id,
u8 type, u8 index, u16 addr, u32 *data);
+int opae_mgr_get_board_info(struct opae_manager *mgr,
+ struct opae_board_info **info);
#endif /* _OPAE_HW_API_H_*/