crypto/qat: add Chacha-Poly in UCS-SPC mode

This commit adds Chacha20-Poly1305 aglorithm that works
in UCS (Unified crypto slice) SPC(Single-Pass) mode.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>

diff --git a/drivers/crypto/qat/qat_sym_capabilities.h b/drivers/crypto/qat/qat_sym_capabilities.h
index fc8e667..5c6e723 100644 (file)
--- a/drivers/crypto/qat/qat_sym_capabilities.h
+++ b/drivers/crypto/qat/qat_sym_capabilities.h
@@ -1144,7 +1144,37 @@
                                },                                      \
                        }, }                                            \
                }, }                                                    \
-       }                                                               \
+       },                                                              \
+       {       /* Chacha20-Poly1305 */                                 \
+       .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,                     \
+               {.sym = {                                               \
+                       .xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,        \
+                       {.aead = {                                      \
+                               .algo = RTE_CRYPTO_AEAD_CHACHA20_POLY1305, \
+                               .block_size = 64,                       \
+                               .key_size = {                           \
+                                       .min = 32,                      \
+                                       .max = 32,                      \
+                                       .increment = 0                  \
+                               },                                      \
+                               .digest_size = {                        \
+                                       .min = 16,                      \
+                                       .max = 16,                      \
+                                       .increment = 0                  \
+                               },                                      \
+                               .aad_size = {                           \
+                                       .min = 0,                       \
+                                       .max = 240,                     \
+                                       .increment = 1                  \
+                               },                                      \
+                               .iv_size = {                            \
+                                       .min = 12,                      \
+                                       .max = 12,                      \
+                                       .increment = 0                  \
+                               },                                      \
+                       }, }                                            \
+               }, }                                                    \
+       }
 
 
 

diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c
index 04bc2d7..6b87fc0 100644 (file)
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -922,6 +922,8 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,
        case RTE_CRYPTO_AEAD_CHACHA20_POLY1305:
                if (aead_xform->key.length != ICP_QAT_HW_CHACHAPOLY_KEY_SZ)
                        return -EINVAL;
+               if (qat_dev_gen == QAT_GEN4)
+                       session->is_ucs = 1;
                session->qat_cipher_alg =
                                ICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305;
                qat_sym_session_handle_single_pass(session,