net/mlx5: fix setting of Rx hash fields
authorDekel Peled <dekelp@mellanox.com>
Wed, 18 Dec 2019 10:05:46 +0000 (12:05 +0200)
committerFerruh Yigit <ferruh.yigit@intel.com>
Fri, 17 Jan 2020 18:45:23 +0000 (19:45 +0100)
Rx hash fields were copied from input parameter into TIR attributes
directly, with no translation. As result the copied value was wrong.

This patch adds translation of value from input bitmap to the
appropriate format.

Fixes: dc9ceff73c99 ("net/mlx5: create advanced RxQ via DevX")
Cc: stable@dpdk.org
Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
drivers/net/mlx5/mlx5_flow.h
drivers/net/mlx5/mlx5_rxq.c

index 08e223e..27d82ac 100644 (file)
@@ -282,6 +282,27 @@ enum mlx5_feature_name {
 /* IBV hash source bits  for IPV6. */
 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
 
+/* IBV hash bits for L3 SRC. */
+#define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
+
+/* IBV hash bits for L3 DST. */
+#define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
+
+/* IBV hash bits for TCP. */
+#define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
+                             IBV_RX_HASH_DST_PORT_TCP)
+
+/* IBV hash bits for UDP. */
+#define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
+                             IBV_RX_HASH_DST_PORT_UDP)
+
+/* IBV hash bits for L4 SRC. */
+#define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
+                                IBV_RX_HASH_SRC_PORT_UDP)
+
+/* IBV hash bits for L4 DST. */
+#define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
+                                IBV_RX_HASH_DST_PORT_UDP)
 
 /* Geneve header first 16Bit */
 #define MLX5_GENEVE_VER_MASK 0x3
index bbc07db..ca25e32 100644 (file)
@@ -36,6 +36,7 @@
 #include "mlx5_autoconf.h"
 #include "mlx5_defs.h"
 #include "mlx5_glue.h"
+#include "mlx5_flow.h"
 
 /* Default RSS hash key also used for ConnectX-3. */
 uint8_t rss_hash_default_key[] = {
@@ -2459,6 +2460,7 @@ mlx5_hrxq_new(struct rte_eth_dev *dev,
                }
        } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
                struct mlx5_devx_tir_attr tir_attr;
+               struct mlx5_rx_hash_field_select *rx_hash_field_select;
                uint32_t i;
                uint32_t lro = 1;
 
@@ -2472,8 +2474,31 @@ mlx5_hrxq_new(struct rte_eth_dev *dev,
                memset(&tir_attr, 0, sizeof(tir_attr));
                tir_attr.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
                tir_attr.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
-               memcpy(&tir_attr.rx_hash_field_selector_outer, &hash_fields,
-                      sizeof(uint64_t));
+#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
+               tir_attr.tunneled_offload_en = !!tunnel;
+               /* Translate hash_fields bitmap to PRM format. */
+               rx_hash_field_select = hash_fields & IBV_RX_HASH_INNER ?
+                                      &tir_attr.rx_hash_field_selector_inner :
+                                      &tir_attr.rx_hash_field_selector_outer;
+#else
+               rx_hash_field_select = &tir_attr.rx_hash_field_selector_outer;
+#endif
+               /* 1 bit: 0: IPv4, 1: IPv6. */
+               rx_hash_field_select->l3_prot_type =
+                       !!(hash_fields & MLX5_IPV6_IBV_RX_HASH);
+               /* 1 bit: 0: TCP, 1: UDP. */
+               rx_hash_field_select->l4_prot_type =
+                       !!(hash_fields & MLX5_UDP_IBV_RX_HASH);
+               /* Bitmask which sets which fields to use in RX Hash. */
+               rx_hash_field_select->selected_fields =
+                       ((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) <<
+                        MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |
+                       (!!(hash_fields & MLX5_L3_DST_IBV_RX_HASH)) <<
+                        MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP |
+                       (!!(hash_fields & MLX5_L4_SRC_IBV_RX_HASH)) <<
+                        MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT |
+                       (!!(hash_fields & MLX5_L4_DST_IBV_RX_HASH)) <<
+                        MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT;
                if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
                        tir_attr.transport_domain = priv->sh->td->id;
                else