]> git.droids-corp.org - dpdk.git/commitdiff
net/ice/base: add more macros for FDID priority
authorQi Zhang <qi.z.zhang@intel.com>
Mon, 30 Mar 2020 11:45:23 +0000 (19:45 +0800)
committerFerruh Yigit <ferruh.yigit@intel.com>
Tue, 21 Apr 2020 11:57:05 +0000 (13:57 +0200)
Add macro for FDID  priority 0 and 3, also adjust the
fdid_prio position to sync with kernel driver.

Signed-off-by: Beilei Xing <beilei.xing@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
drivers/net/ice/base/ice_fdir.h
drivers/net/ice/base/ice_lan_tx_rx.h

index 86b532b7343a9fc44870304606d320f67c311222..6f11195f6278b51d49f9f33144a2cec4f211d58f 100644 (file)
@@ -202,8 +202,8 @@ struct ice_fdir_fltr {
        u8 cnt_ena;
        u8 fltr_status;
        u16 cnt_index;
-       u8 fdid_prio;
        u32 fltr_id;
+       u8 fdid_prio;
        /* Set to true for an ACL filter */
        bool acl_fltr;
 };
index 331297462e446188e6ac3b8dbd4004b3cdda9efd..d904385cb6376b582549bd2873f3ca368a58a01c 100644 (file)
@@ -162,7 +162,9 @@ struct ice_fltr_desc {
 
 #define ICE_FXD_FLTR_QW1_FDID_PRI_S    25
 #define ICE_FXD_FLTR_QW1_FDID_PRI_M    (0x7ULL << ICE_FXD_FLTR_QW1_FDID_PRI_S)
+#define ICE_FXD_FLTR_QW1_FDID_PRI_ZERO 0x0ULL
 #define ICE_FXD_FLTR_QW1_FDID_PRI_ONE  0x1ULL
+#define ICE_FXD_FLTR_QW1_FDID_PRI_THREE        0x3ULL
 
 #define ICE_FXD_FLTR_QW1_FDID_MDID_S   28
 #define ICE_FXD_FLTR_QW1_FDID_MDID_M   (0xFULL << ICE_FXD_FLTR_QW1_FDID_MDID_S)