SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_template_db.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_utils.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_mapper.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_matcher.c
#
# Export include files
#define BNXT_ULP_TX_NUM_FLOWS 32
#define BNXT_ULP_TX_TBL_IF_ID 0
+enum bnxt_tf_rc {
+ BNXT_TF_RC_PARSE_ERR = -2,
+ BNXT_TF_RC_ERROR = -1,
+ BNXT_TF_RC_SUCCESS = 0
+};
+
+/* ulp direction Type */
+enum ulp_direction_type {
+ ULP_DIR_INGRESS,
+ ULP_DIR_EGRESS,
+};
+
struct bnxt_ulp_mark_tbl *
bnxt_ulp_cntxt_ptr2_mark_db_get(struct bnxt_ulp_context *ulp_ctx);
--- /dev/null
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2020 Broadcom
+ * All rights reserved.
+ */
+
+#include "ulp_matcher.h"
+#include "ulp_utils.h"
+
+/* Utility function to check if bitmap is zero */
+static inline
+int ulp_field_mask_is_zero(uint8_t *bitmap, uint32_t size)
+{
+ while (size-- > 0) {
+ if (*bitmap != 0)
+ return 0;
+ bitmap++;
+ }
+ return 1;
+}
+
+/* Utility function to check if bitmap is all ones */
+static inline int
+ulp_field_mask_is_ones(uint8_t *bitmap, uint32_t size)
+{
+ while (size-- > 0) {
+ if (*bitmap != 0xFF)
+ return 0;
+ bitmap++;
+ }
+ return 1;
+}
+
+/* Utility function to check if bitmap is non zero */
+static inline int
+ulp_field_mask_notzero(uint8_t *bitmap, uint32_t size)
+{
+ while (size-- > 0) {
+ if (*bitmap != 0)
+ return 1;
+ bitmap++;
+ }
+ return 0;
+}
+
+/* Utility function to mask the computed and internal proto headers. */
+static void
+ulp_matcher_hdr_fields_normalize(struct ulp_rte_hdr_bitmap *hdr1,
+ struct ulp_rte_hdr_bitmap *hdr2)
+{
+ /* copy the contents first */
+ rte_memcpy(hdr2, hdr1, sizeof(struct ulp_rte_hdr_bitmap));
+
+ /* reset the computed fields */
+ ULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_SVIF);
+ ULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_OO_VLAN);
+ ULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_OI_VLAN);
+ ULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_IO_VLAN);
+ ULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_II_VLAN);
+ ULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_O_L3);
+ ULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_O_L4);
+ ULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_I_L3);
+ ULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_I_L4);
+}
+
+/*
+ * Function to handle the matching of RTE Flows and validating
+ * the pattern masks against the flow templates.
+ */
+int32_t
+ulp_matcher_pattern_match(enum ulp_direction_type dir,
+ struct ulp_rte_hdr_bitmap *hdr_bitmap,
+ struct ulp_rte_hdr_field *hdr_field,
+ struct ulp_rte_act_bitmap *act_bitmap,
+ uint32_t *class_id)
+{
+ struct bnxt_ulp_header_match_info *sel_hdr_match;
+ uint32_t hdr_num, idx, jdx;
+ uint32_t match = 0;
+ struct ulp_rte_hdr_bitmap hdr_bitmap_masked;
+ uint32_t start_idx;
+ struct ulp_rte_hdr_field *m_field;
+ struct bnxt_ulp_matcher_field_info *sf;
+
+ /* Select the ingress or egress template to match against */
+ if (dir == ULP_DIR_INGRESS) {
+ sel_hdr_match = ulp_ingress_hdr_match_list;
+ hdr_num = BNXT_ULP_INGRESS_HDR_MATCH_SZ;
+ } else {
+ sel_hdr_match = ulp_egress_hdr_match_list;
+ hdr_num = BNXT_ULP_EGRESS_HDR_MATCH_SZ;
+ }
+
+ /* Remove the hdr bit maps that are internal or computed */
+ ulp_matcher_hdr_fields_normalize(hdr_bitmap, &hdr_bitmap_masked);
+
+ /* Loop through the list of class templates to find the match */
+ for (idx = 0; idx < hdr_num; idx++, sel_hdr_match++) {
+ if (ULP_BITSET_CMP(&sel_hdr_match->hdr_bitmap,
+ &hdr_bitmap_masked)) {
+ /* no match found */
+ BNXT_TF_DBG(DEBUG, "Pattern Match failed template=%d\n",
+ idx);
+ continue;
+ }
+ match = ULP_BITMAP_ISSET(act_bitmap->bits,
+ BNXT_ULP_ACTION_BIT_VNIC);
+ if (match != sel_hdr_match->act_vnic) {
+ /* no match found */
+ BNXT_TF_DBG(DEBUG, "Vnic Match failed template=%d\n",
+ idx);
+ continue;
+ } else {
+ match = 1;
+ }
+
+ /* Found a matching hdr bitmap, match the fields next */
+ start_idx = sel_hdr_match->start_idx;
+ for (jdx = 0; jdx < sel_hdr_match->num_entries; jdx++) {
+ m_field = &hdr_field[jdx + BNXT_ULP_HDR_FIELD_LAST - 1];
+ sf = &ulp_field_match[start_idx + jdx];
+ switch (sf->mask_opcode) {
+ case BNXT_ULP_FMF_MASK_ANY:
+ match &= ulp_field_mask_is_zero(m_field->mask,
+ m_field->size);
+ break;
+ case BNXT_ULP_FMF_MASK_EXACT:
+ match &= ulp_field_mask_is_ones(m_field->mask,
+ m_field->size);
+ break;
+ case BNXT_ULP_FMF_MASK_WILDCARD:
+ match &= ulp_field_mask_notzero(m_field->mask,
+ m_field->size);
+ break;
+ case BNXT_ULP_FMF_MASK_IGNORE:
+ default:
+ break;
+ }
+ if (!match)
+ break;
+ }
+ if (match) {
+ BNXT_TF_DBG(DEBUG,
+ "Found matching pattern template %d\n",
+ sel_hdr_match->class_tmpl_id);
+ *class_id = sel_hdr_match->class_tmpl_id;
+ return BNXT_TF_RC_SUCCESS;
+ }
+ }
+ BNXT_TF_DBG(DEBUG, "Did not find any matching template\n");
+ *class_id = 0;
+ return BNXT_TF_RC_ERROR;
+}
--- /dev/null
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2020 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef ULP_MATCHER_H_
+#define ULP_MATCHER_H_
+
+#include <rte_log.h>
+#include "bnxt.h"
+#include "ulp_template_db.h"
+#include "ulp_template_struct.h"
+#include "bnxt_tf_common.h"
+
+/*
+ * Function to handle the matching of RTE Flows and validating
+ * the pattern masks against the flow templates.
+ */
+int32_t
+ulp_matcher_pattern_match(enum ulp_direction_type dir,
+ struct ulp_rte_hdr_bitmap *hdr_bitmap,
+ struct ulp_rte_hdr_field *hdr_field,
+ struct ulp_rte_act_bitmap *act_bitmap,
+ uint32_t *class_id);
+
+#endif /* ULP_MATCHER_H_ */
}
};
+struct bnxt_ulp_header_match_info ulp_ingress_hdr_match_list[] = {
+ {
+ .hdr_bitmap = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP },
+ .start_idx = 0,
+ .num_entries = 24,
+ .class_tmpl_id = 0,
+ .act_vnic = 0
+ }
+};
+
+struct bnxt_ulp_header_match_info ulp_egress_hdr_match_list[] = {
+};
+
+struct bnxt_ulp_matcher_field_info ulp_field_match[] = {
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ },
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_EXACT,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ },
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_EXACT,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ },
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ },
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ },
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ },
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ },
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ },
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ },
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ },
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ },
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_ANY,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ },
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ },
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ },
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ },
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_ANY,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ },
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ },
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ },
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_EXACT,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ },
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_EXACT,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ },
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_EXACT,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ },
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_EXACT,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ },
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ },
+ {
+ .mask_opcode = BNXT_ULP_FMF_MASK_IGNORE,
+ .spec_opcode = BNXT_ULP_FMF_SPEC_IGNORE
+ }
+};
+
struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
{
.field_bit_size = 10,
#define BNXT_ULP_MAX_NUM_DEVICES 4
#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
+#define BNXT_ULP_INGRESS_HDR_MATCH_SZ 2
+#define BNXT_ULP_EGRESS_HDR_MATCH_SZ 1
enum bnxt_ulp_action_bit {
BNXT_ULP_ACTION_BIT_MARK = 0x0000000000000001,
BNXT_ULP_ACTION_BIT_LAST = 0x0000000008000000
};
+enum bnxt_ulp_hdr_bit {
+ BNXT_ULP_HDR_BIT_SVIF = 0x0000000000000001,
+ BNXT_ULP_HDR_BIT_O_ETH = 0x0000000000000002,
+ BNXT_ULP_HDR_BIT_OO_VLAN = 0x0000000000000004,
+ BNXT_ULP_HDR_BIT_OI_VLAN = 0x0000000000000008,
+ BNXT_ULP_HDR_BIT_O_L3 = 0x0000000000000010,
+ BNXT_ULP_HDR_BIT_O_IPV4 = 0x0000000000000020,
+ BNXT_ULP_HDR_BIT_O_IPV6 = 0x0000000000000040,
+ BNXT_ULP_HDR_BIT_O_L4 = 0x0000000000000080,
+ BNXT_ULP_HDR_BIT_O_TCP = 0x0000000000000100,
+ BNXT_ULP_HDR_BIT_O_UDP = 0x0000000000000200,
+ BNXT_ULP_HDR_BIT_T_VXLAN = 0x0000000000000400,
+ BNXT_ULP_HDR_BIT_T_GRE = 0x0000000000000800,
+ BNXT_ULP_HDR_BIT_I_ETH = 0x0000000000001000,
+ BNXT_ULP_HDR_BIT_IO_VLAN = 0x0000000000002000,
+ BNXT_ULP_HDR_BIT_II_VLAN = 0x0000000000004000,
+ BNXT_ULP_HDR_BIT_I_L3 = 0x0000000000008000,
+ BNXT_ULP_HDR_BIT_I_IPV4 = 0x0000000000010000,
+ BNXT_ULP_HDR_BIT_I_IPV6 = 0x0000000000020000,
+ BNXT_ULP_HDR_BIT_I_L4 = 0x0000000000040000,
+ BNXT_ULP_HDR_BIT_I_TCP = 0x0000000000080000,
+ BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000100000,
+ BNXT_ULP_HDR_BIT_LAST = 0x0000000000200000
+};
+
enum bnxt_ulp_byte_order {
BNXT_ULP_BYTE_ORDER_BE,
BNXT_ULP_BYTE_ORDER_LE,
BNXT_ULP_FMF_MASK_LAST
};
+enum bnxt_ulp_fmf_spec {
+ BNXT_ULP_FMF_SPEC_IGNORE = 0,
+ BNXT_ULP_FMF_SPEC_LAST = 1
+};
+
enum bnxt_ulp_mark_enable {
BNXT_ULP_MARK_ENABLE_NO = 0,
BNXT_ULP_MARK_ENABLE_YES = 1,
BNXT_ULP_MARK_ENABLE_LAST = 2
};
+enum bnxt_ulp_hdr_field {
+ BNXT_ULP_HDR_FIELD_MPLS_TAG_NUM = 0,
+ BNXT_ULP_HDR_FIELD_O_VTAG_NUM = 1,
+ BNXT_ULP_HDR_FIELD_I_VTAG_NUM = 2,
+ BNXT_ULP_HDR_FIELD_SVIF_INDEX = 3,
+ BNXT_ULP_HDR_FIELD_LAST = 4
+};
+
enum bnxt_ulp_mask_opc {
BNXT_ULP_MASK_OPC_SET_TO_CONSTANT = 0,
BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD = 1,
uint32_t size;
};
+struct bnxt_ulp_matcher_field_info {
+ enum bnxt_ulp_fmf_mask mask_opcode;
+ enum bnxt_ulp_fmf_spec spec_opcode;
+};
+
struct ulp_rte_act_bitmap {
uint64_t bits;
};
uint8_t act_details[BNXT_ULP_ACT_PROP_IDX_LAST];
};
+/* Flow Matcher structures */
+struct bnxt_ulp_header_match_info {
+ struct ulp_rte_hdr_bitmap hdr_bitmap;
+ uint32_t start_idx;
+ uint32_t num_entries;
+ uint32_t class_tmpl_id;
+ uint32_t act_vnic;
+};
+
+/* Flow Matcher templates Structure Array defined in template source*/
+extern struct bnxt_ulp_header_match_info ulp_ingress_hdr_match_list[];
+extern struct bnxt_ulp_header_match_info ulp_egress_hdr_match_list[];
+
+/* Flow field match Information Structure Array defined in template source*/
+extern struct bnxt_ulp_matcher_field_info ulp_field_match[];
+
/* Device specific parameters */
struct bnxt_ulp_device_params {
uint8_t description[16];
git.droids-corp.org / dpdk.git / commitdiff