net/cxgbe: add compressed error vector

Add support for compressed error vector available in cpl_rx_pkt for
Chelsio T6.

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>

diff --git a/drivers/net/cxgbe/base/common.h b/drivers/net/cxgbe/base/common.h
index 5765bf3..1eda57d 100644 (file)
--- a/drivers/net/cxgbe/base/common.h
+++ b/drivers/net/cxgbe/base/common.h
@@ -157,6 +157,11 @@ struct tp_params {
        u32 vlan_pri_map;               /* cached TP_VLAN_PRI_MAP */
        u32 ingress_config;             /* cached TP_INGRESS_CONFIG */
 
+       /* cached TP_OUT_CONFIG compressed error vector
+        * and passing outer header info for encapsulated packets.
+        */
+       int rx_pkt_encap;
+
        /*
         * TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets.  This is a
         * subset of the set of fields which may be present in the Compressed

diff --git a/drivers/net/cxgbe/base/t4_hw.c b/drivers/net/cxgbe/base/t4_hw.c
index 96d4bfd..94abd5b 100644 (file)
--- a/drivers/net/cxgbe/base/t4_hw.c
+++ b/drivers/net/cxgbe/base/t4_hw.c
@@ -4594,6 +4594,14 @@ int t4_init_tp_params(struct adapter *adap)
                         &adap->params.tp.ingress_config, 1,
                         A_TP_INGRESS_CONFIG);
 
+       /* For T6, cache the adapter's compressed error vector
+        * and passing outer header info for encapsulated packets.
+        */
+       if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
+               v = t4_read_reg(adap, A_TP_OUT_CONFIG);
+               adap->params.tp.rx_pkt_encap = (v & F_CRXPKTENC) ? 1 : 0;
+       }
+
        /*
         * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
         * shift positions of several elements of the Compressed Filter Tuple

diff --git a/drivers/net/cxgbe/base/t4_msg.h b/drivers/net/cxgbe/base/t4_msg.h
index 4b04cd0..6acd749 100644 (file)
--- a/drivers/net/cxgbe/base/t4_msg.h
+++ b/drivers/net/cxgbe/base/t4_msg.h
@@ -1,7 +1,7 @@
 /*-
  *   BSD LICENSE
  *
- *   Copyright(c) 2014-2015 Chelsio Communications.
+ *   Copyright(c) 2014-2017 Chelsio Communications.
  *   All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
@@ -262,6 +262,20 @@ struct cpl_rx_pkt {
 #define V_RXF_IP6(x) ((x) << S_RXF_IP6)
 #define F_RXF_IP6    V_RXF_IP6(1U)
 
+/* rx_pkt.err_vec fields */
+/* In T6, rx_pkt.err_vec indicates
+ * RxError Error vector (16b) or
+ * Encapsulating header length (8b),
+ * Outer encapsulation type (2b) and
+ * compressed error vector (6b) if CRxPktEnc is
+ * enabled in TP_OUT_CONFIG
+ */
+#define S_T6_COMPR_RXERR_VEC    0
+#define M_T6_COMPR_RXERR_VEC    0x3F
+#define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_VEC)
+#define G_T6_COMPR_RXERR_VEC(x) \
+       (((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC)
+
 /* cpl_fw*.type values */
 enum {
        FW_TYPE_RSSCPL = 4,

diff --git a/drivers/net/cxgbe/base/t4_regs.h b/drivers/net/cxgbe/base/t4_regs.h
index eb23614..8dc1f58 100644 (file)
--- a/drivers/net/cxgbe/base/t4_regs.h
+++ b/drivers/net/cxgbe/base/t4_regs.h
@@ -443,6 +443,12 @@
 #define F_UPCRST    V_UPCRST(1U)
 
 /* registers for module TP */
+#define A_TP_OUT_CONFIG 0x7d04
+
+#define S_CRXPKTENC    3
+#define V_CRXPKTENC(x) ((x) << S_CRXPKTENC)
+#define F_CRXPKTENC    V_CRXPKTENC(1U)
+
 #define TP_BASE_ADDR 0x7d00
 
 #define A_TP_TIMER_RESOLUTION 0x7d90

diff --git a/drivers/net/cxgbe/sge.c b/drivers/net/cxgbe/sge.c
index b16a0bf..020879a 100644 (file)
--- a/drivers/net/cxgbe/sge.c
+++ b/drivers/net/cxgbe/sge.c
@@ -1352,10 +1352,16 @@ int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
        const struct rss_header *rss_hdr;
        bool csum_ok;
        struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);
+       u16 err_vec;
 
        rss_hdr = (const void *)rsp;
        pkt = (const void *)&rsp[1];
-       csum_ok = pkt->csum_calc && !pkt->err_vec;
+       /* Compressed error vector is enabled for T6 only */
+       if (q->adapter->params.tp.rx_pkt_encap)
+               err_vec = G_T6_COMPR_RXERR_VEC(ntohs(pkt->err_vec));
+       else
+               err_vec = ntohs(pkt->err_vec);
+       csum_ok = pkt->csum_calc && !err_vec;
 
        mbuf = t4_pktgl_to_mbuf(si);
        if (unlikely(!mbuf)) {
@@ -1466,9 +1472,10 @@ static int process_responses(struct sge_rspq *q, int budget,
                                                (const void *)q->cur_desc;
                        const struct cpl_rx_pkt *cpl =
                                                (const void *)&q->cur_desc[1];
-                       bool csum_ok = cpl->csum_calc && !cpl->err_vec;
                        struct rte_mbuf *pkt, *npkt;
                        u32 len, bufsz;
+                       bool csum_ok;
+                       u16 err_vec;
 
                        len = ntohl(rc->pldbuflen_qid);
                        BUG_ON(!(len & F_RSPD_NEWBUF));
@@ -1477,6 +1484,16 @@ static int process_responses(struct sge_rspq *q, int budget,
                        len = G_RSPD_LEN(len);
                        pkt->pkt_len = len;
 
+                       /* Compressed error vector is enabled for
+                        * T6 only
+                        */
+                       if (q->adapter->params.tp.rx_pkt_encap)
+                               err_vec = G_T6_COMPR_RXERR_VEC(
+                                               ntohs(cpl->err_vec));
+                       else
+                               err_vec = ntohs(cpl->err_vec);
+                       csum_ok = cpl->csum_calc && !err_vec;
+
                        /* Chain mbufs into len if necessary */
                        while (len) {
                                struct rte_mbuf *new_pkt = rsd->buf;