common/octeontx2: support CNF95xx SoC

Update platform support of CNF95xx in documentation and
also, update the HW cap based on PCI subsystem id and revision id.
This patch also changes HW capability handling to be based on
PCI Revision ID. PCI Revision ID contains a unique identifier
to identify chip, major and minor revisions.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>

diff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst
index 97c631f3bec6acfbda3e328cedd28cada9568795..f5be973a58afa5c9af4eaae01b2659642f596d8a 100644 (file)
--- a/doc/guides/platform/octeontx2.rst
+++ b/doc/guides/platform/octeontx2.rst
@@ -15,6 +15,7 @@ Supported OCTEON TX2 SoCs
 
 - CN96xx
 - CN93xx
+- CNF95xx
 
 OCTEON TX2 Resource Virtualization Unit architecture
 ----------------------------------------------------

diff --git a/drivers/common/octeontx2/otx2_common.h b/drivers/common/octeontx2/otx2_common.h
index cdb25d9ed2039971988afcb577f235ee15227f63..faf206b3c7411da544d15b76b17c44adae2f291e 100644 (file)
--- a/drivers/common/octeontx2/otx2_common.h
+++ b/drivers/common/octeontx2/otx2_common.h
@@ -108,6 +108,26 @@ extern int otx2_logtype_dpi;
 #define PCI_DEVID_OCTEONTX2_RVU_AF_VF          0xA0f8
 #define PCI_DEVID_OCTEONTX2_DPI_VF             0xA081
 
+/* Subsystem Device ID */
+#define PCI_SUBSYS_DEVID_96XX_95XX             0xB200
+
+/*
+ * REVID for RVU PCIe devices.
+ * Bits 0..1: minor pass
+ * Bits 3..2: major pass
+ * Bits 7..4: midr id, 0:96, 1:95, 2:loki, f:unknown
+ */
+
+#define RVU_PCI_REV_MIDR_ID(rev_id)            (rev_id >> 4)
+#define RVU_PCI_REV_MAJOR(rev_id)              ((rev_id >> 2) & 0x3)
+#define RVU_PCI_REV_MINOR(rev_id)              (rev_id & 0x3)
+
+#define RVU_PCI_CN96XX_MIDR_ID                 0x0
+#define RVU_PCI_CNF95XX_MIDR_ID                        0x1
+
+/* PCI Config offsets */
+#define RVU_PCI_REVISION_ID                    0x08
+
 /* IO Access */
 #define otx2_read64(addr) rte_read64_relaxed((void *)(addr))
 #define otx2_write64(val, addr) rte_write64_relaxed((val), (void *)(addr))

diff --git a/drivers/common/octeontx2/otx2_dev.c b/drivers/common/octeontx2/otx2_dev.c
index 3b51fa93ad298230209fdf65c1753bae5dce0b43..f58a6e72593741b622e7cf7bcf896aa33cd5380b 100644 (file)
--- a/drivers/common/octeontx2/otx2_dev.c
+++ b/drivers/common/octeontx2/otx2_dev.c
@@ -875,20 +875,9 @@ otx2_dev_active_vfs(void *otx2_dev)
        return count;
 }
 
-static void
-otx2_update_pass_hwcap(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
-{
-       RTE_SET_USED(pci_dev);
-
-       /* Update this logic when we have A1 */
-       dev->hwcap |= OTX2_HWCAP_F_A0;
-}
-
 static void
 otx2_update_vf_hwcap(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
 {
-       dev->hwcap = 0;
-
        switch (pci_dev->id.device_id) {
        case PCI_DEVID_OCTEONTX2_RVU_PF:
                break;
@@ -907,7 +896,7 @@ otx2_update_vf_hwcap(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
  * Initialize the otx2 device
  */
 int
-otx2_dev_init(struct rte_pci_device *pci_dev, void *otx2_dev)
+otx2_dev_priv_init(struct rte_pci_device *pci_dev, void *otx2_dev)
 {
        int up_direction = MBOX_DIR_PFAF_UP;
        int rc, direction = MBOX_DIR_PFAF;
@@ -931,7 +920,6 @@ otx2_dev_init(struct rte_pci_device *pci_dev, void *otx2_dev)
        dev->bar4 = bar4;
 
        otx2_update_vf_hwcap(pci_dev, dev);
-       otx2_update_pass_hwcap(pci_dev, dev);
 
        if (otx2_dev_is_vf(dev)) {
                direction = MBOX_DIR_VFPF;

diff --git a/drivers/common/octeontx2/otx2_dev.h b/drivers/common/octeontx2/otx2_dev.h
index be862ad1b4163d9819ecac9a28c02e5133e25a6d..53a3669526a725100bc689d2adbfeee986ad560b 100644 (file)
--- a/drivers/common/octeontx2/otx2_dev.h
+++ b/drivers/common/octeontx2/otx2_dev.h
@@ -13,14 +13,18 @@
 #include "otx2_mempool.h"
 
 /* Common HWCAP flags. Use from LSB bits */
-#define OTX2_HWCAP_F_VF                BIT_ULL(0) /* VF device */
+#define OTX2_HWCAP_F_VF                BIT_ULL(8) /* VF device */
 #define otx2_dev_is_vf(dev)    (dev->hwcap & OTX2_HWCAP_F_VF)
 #define otx2_dev_is_pf(dev)    (!(dev->hwcap & OTX2_HWCAP_F_VF))
 #define otx2_dev_is_lbk(dev)   ((dev->hwcap & OTX2_HWCAP_F_VF) && \
                                 (dev->tx_chan_base < 0x700))
+#define otx2_dev_revid(dev)    (dev->hwcap & 0xFF)
 
-#define OTX2_HWCAP_F_A0                BIT_ULL(1) /* A0 device */
-#define otx2_dev_is_A0(dev)    (dev->hwcap & OTX2_HWCAP_F_A0)
+#define otx2_dev_is_A0(dev)                                    \
+       ((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0) &&     \
+        (RVU_PCI_REV_MINOR(otx2_dev_revid(dev)) == 0x0))
+#define otx2_dev_is_Ax(dev)                                    \
+       ((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0))
 
 struct otx2_dev;
 
@@ -61,7 +65,32 @@ struct otx2_dev {
        OTX2_DEV;
 };
 
-int otx2_dev_init(struct rte_pci_device *pci_dev, void *otx2_dev);
+int otx2_dev_priv_init(struct rte_pci_device *pci_dev, void *otx2_dev);
+
+/* Common dev init and fini routines */
+
+static __rte_always_inline int
+otx2_dev_init(struct rte_pci_device *pci_dev, void *otx2_dev)
+{
+       struct otx2_dev *dev = otx2_dev;
+       uint8_t rev_id;
+       int rc;
+
+       rc = rte_pci_read_config(pci_dev, &rev_id,
+                                1, RVU_PCI_REVISION_ID);
+       if (rc != 1) {
+               otx2_err("Failed to read pci revision id, rc=%d", rc);
+               return rc;
+       }
+
+       if (pci_dev->id.subsystem_device_id == PCI_SUBSYS_DEVID_96XX_95XX)
+               dev->hwcap = rev_id;
+       else
+               dev->hwcap = 0;
+
+       return otx2_dev_priv_init(pci_dev, otx2_dev);
+}
+
 void otx2_dev_fini(struct rte_pci_device *pci_dev, void *otx2_dev);
 int otx2_dev_active_vfs(void *otx2_dev);
 

diff --git a/drivers/common/octeontx2/rte_common_octeontx2_version.map b/drivers/common/octeontx2/rte_common_octeontx2_version.map
index 2f4826311deadf832e7912a42f51075f193f8196..4400120da00b9da116b748f43efa7925d2cc82b0 100644 (file)
--- a/drivers/common/octeontx2/rte_common_octeontx2_version.map
+++ b/drivers/common/octeontx2/rte_common_octeontx2_version.map
@@ -3,7 +3,7 @@ DPDK_19.08 {
 
        otx2_dev_active_vfs;
        otx2_dev_fini;
-       otx2_dev_init;
+       otx2_dev_priv_init;
 
        otx2_logtype_base;
        otx2_logtype_dpi;

diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c
index 156e7d34f809cd05846baf773e36dad6a743cba1..fcb1869d5871678fcc4741cae7d3f59815a8c369 100644 (file)
--- a/drivers/net/octeontx2/otx2_ethdev.c
+++ b/drivers/net/octeontx2/otx2_ethdev.c
@@ -1235,7 +1235,7 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)
                nix_lf_free(dev);
        }
 
-       if (otx2_dev_is_A0(dev) &&
+       if (otx2_dev_is_Ax(dev) &&
            (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
            ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
            (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
@@ -1787,7 +1787,7 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
        dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
        dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
 
-       if (otx2_dev_is_A0(dev)) {
+       if (otx2_dev_is_Ax(dev)) {
                dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
                dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
        }

diff --git a/drivers/net/octeontx2/otx2_flow_ctrl.c b/drivers/net/octeontx2/otx2_flow_ctrl.c
index 0392086d8952a3ae44687842eec4e979671521fb..ae5635204c122f40c68287808c2cb6f2f3af82f0 100644 (file)
--- a/drivers/net/octeontx2/otx2_flow_ctrl.c
+++ b/drivers/net/octeontx2/otx2_flow_ctrl.c
@@ -162,8 +162,8 @@ otx2_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
 
        /* Check if TX pause frame is already enabled or not */
        if (fc->tx_pause ^ tx_pause) {
-               if (otx2_dev_is_A0(dev) && eth_dev->data->dev_started) {
-                       /* on A0, CQ should be in disabled state
+               if (otx2_dev_is_Ax(dev) && eth_dev->data->dev_started) {
+                       /* on Ax, CQ should be in disabled state
                         * while setting flow control configuration.
                         */
                        otx2_info("Stop the port=%d for setting flow control\n",
@@ -207,8 +207,8 @@ otx2_nix_update_flow_ctrl_mode(struct rte_eth_dev *eth_dev)
         */
        otx2_nix_flow_ctrl_get(eth_dev, &fc_conf);
 
-       /* To avoid Link credit deadlock on A0, disable Tx FC if it's enabled */
-       if (otx2_dev_is_A0(dev) &&
+       /* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */
+       if (otx2_dev_is_Ax(dev) &&
            (fc_conf.mode == RTE_FC_FULL || fc_conf.mode == RTE_FC_RX_PAUSE)) {
                fc_conf.mode =
                                (fc_conf.mode == RTE_FC_FULL ||

diff --git a/drivers/net/octeontx2/otx2_tm.c b/drivers/net/octeontx2/otx2_tm.c
index 24692069532be4f863f0317d6ec2c1336c2c4190..12903ec1b8dcef8530355b70721371f56333395e 100644 (file)
--- a/drivers/net/octeontx2/otx2_tm.c
+++ b/drivers/net/octeontx2/otx2_tm.c
@@ -59,7 +59,7 @@ static bool
 nix_tm_have_tl1_access(struct otx2_eth_dev *dev)
 {
        bool is_lbk = otx2_dev_is_lbk(dev);
-       return otx2_dev_is_pf(dev) && !otx2_dev_is_A0(dev) &&
+       return otx2_dev_is_pf(dev) && !otx2_dev_is_Ax(dev) &&
                !is_lbk && !dev->maxvf;
 }