]> git.droids-corp.org - dpdk.git/commitdiff
net/mlx5: support timestamp format
authorViacheslav Ovsiienko <viacheslavo@nvidia.com>
Sun, 14 Mar 2021 12:12:59 +0000 (12:12 +0000)
committerRaslan Darawsheh <rasland@nvidia.com>
Tue, 16 Mar 2021 09:05:34 +0000 (10:05 +0100)
This patch adds support for the timestamp format settings for
the receive and send queues. If the firmware version x.30.1000
or above is installed and the NIC timestamps are configured
with the real-time format, the default zero values for newly
added fields cause the queue creation to fail.

The patch queries the timestamp formats supported by the hardware
and sets the configuration values in queue context accordingly.

Fixes: 86fc67fc9315 ("net/mlx5: create advanced RxQ object via DevX")
Fixes: ae18a1ae9692 ("net/mlx5: support Tx hairpin queues")
Fixes: 15c3807e86ab ("common/mlx5: support DevX QP operations")
Cc: stable@dpdk.org
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
drivers/net/mlx5/linux/mlx5_os.c
drivers/net/mlx5/mlx5.h
drivers/net/mlx5/mlx5_devx.c
drivers/net/mlx5/mlx5_flow_age.c
drivers/net/mlx5/mlx5_txpp.c
drivers/net/mlx5/windows/mlx5_os.c

index 1217b510b6ae2464c119109787c473776c95899a..5e3ae9f10eb817c43503fe29056ddaa26c37c46b 100644 (file)
@@ -1173,6 +1173,9 @@ err_secondary:
                        sh->cmng.relaxed_ordering_read = 0;
                        sh->cmng.relaxed_ordering_write = 0;
                }
+               sh->rq_ts_format = config->hca_attr.rq_ts_format;
+               sh->sq_ts_format = config->hca_attr.sq_ts_format;
+               sh->qp_ts_format = config->hca_attr.qp_ts_format;
                /* Check for LRO support. */
                if (config->dest_tir && config->hca_attr.lro_cap &&
                    config->dv_flow_en) {
index a281fd20eaf151434ba3c36b77c2aa1ac6243679..14043b68d30651f7c655ae8ef75aba749ca04e29 100644 (file)
@@ -681,6 +681,9 @@ struct mlx5_dev_ctx_shared {
        uint16_t bond_dev; /* Bond primary device id. */
        uint32_t devx:1; /* Opened with DV. */
        uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */
+       uint32_t rq_ts_format:2; /* RQ timestamp formats supported. */
+       uint32_t sq_ts_format:2; /* SQ timestamp formats supported. */
+       uint32_t qp_ts_format:2; /* QP timestamp formats supported. */
        uint32_t max_port; /* Maximal IB device port index. */
        void *ctx; /* Verbs/DV/DevX context. */
        void *pd; /* Protection Domain. */
index 2cb3bd1f12043ea77c201df0e2c0f8c5aedbad7a..5c940edd8835ae98f06d8d8a0e772b0afd2b67df 100644 (file)
@@ -996,8 +996,8 @@ mlx5_txq_create_devx_sq_resources(struct rte_eth_dev *dev, uint16_t idx,
                        .uar_page =
                                 mlx5_os_get_devx_uar_page_id(priv->sh->tx_uar),
                },
+               .ts_format = mlx5_ts_format_conv(priv->sh->sq_ts_format),
        };
-
        /* Create Send Queue object with DevX. */
        return mlx5_devx_sq_create(priv->sh->ctx, &txq_obj->sq_obj, log_desc_n,
                                   &sq_attr, priv->sh->numa_node);
index 3005afdd33cdbd045eee44364ac5ef9f0bef118b..00cb20dd6231392ce404cdab757812452114232a 100644 (file)
@@ -202,7 +202,8 @@ mlx5_aso_init_sq(struct mlx5_aso_sq *sq)
  */
 static int
 mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, int socket,
-                  void *uar, uint32_t pdn,  uint16_t log_desc_n)
+                  void *uar, uint32_t pdn,  uint16_t log_desc_n,
+                  uint32_t ts_format)
 {
        struct mlx5_devx_create_sq_attr attr = {
                .user_index = 0xFFFF,
@@ -210,6 +211,7 @@ mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, int socket,
                        .pd = pdn,
                        .uar_page = mlx5_os_get_devx_uar_page_id(uar),
                },
+               .ts_format = mlx5_ts_format_conv(ts_format),
        };
        struct mlx5_devx_modify_sq_attr modify_attr = {
                .state = MLX5_SQC_STATE_RDY,
@@ -265,7 +267,8 @@ int
 mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh)
 {
        return mlx5_aso_sq_create(sh->ctx, &sh->aso_age_mng->aso_sq, 0,
-                                 sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC);
+                                 sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,
+                                 sh->sq_ts_format);
 }
 
 /**
index 696282ca3153f946c43f346ee21b3685371c00a2..e8d632ad232d77601371f9d2871ed274e54eef40 100644 (file)
@@ -234,6 +234,7 @@ mlx5_txpp_create_rearm_queue(struct mlx5_dev_ctx_shared *sh)
                        .pd = sh->pdn,
                        .uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar),
                },
+               .ts_format = mlx5_ts_format_conv(sh->sq_ts_format),
        };
        struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
        struct mlx5_devx_cq_attr cq_attr = {
@@ -443,6 +444,7 @@ mlx5_txpp_create_clock_queue(struct mlx5_dev_ctx_shared *sh)
        sq_attr.wq_attr.cd_slave = 1;
        sq_attr.wq_attr.uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar);
        sq_attr.wq_attr.pd = sh->pdn;
+       sq_attr.ts_format = mlx5_ts_format_conv(sh->sq_ts_format);
        ret = mlx5_devx_sq_create(sh->ctx, &wq->sq_obj, log2above(wq->sq_size),
                                  &sq_attr, sh->numa_node);
        if (ret) {
index e7db85b7571e6c483adbdd5a4a46355f4fada904..6f392761437562eb271e5fad98d971ed2f331191 100644 (file)
@@ -497,6 +497,9 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
                                                 (NS_PER_S / MS_PER_S))
                                config->rt_timestamp = 1;
                }
+               sh->rq_ts_format = config->hca_attr.rq_ts_format;
+               sh->sq_ts_format = config->hca_attr.sq_ts_format;
+               sh->qp_ts_format = config->hca_attr.qp_ts_format;
        }
        if (config->mprq.enabled) {
                DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");