Cavium OcteonTX
M: Santosh Shukla <santosh.shukla@caviumnetworks.com>
M: Jerin Jacob <jerin.jacob@caviumnetworks.com>
+F: drivers/common/octeontx/
F: drivers/mempool/octeontx/
F: drivers/net/octeontx/
F: doc/guides/nics/octeontx.rst
librte_bus_vdev.so.1
librte_cfgfile.so.2
librte_cmdline.so.2
+ + librte_common_octeontx.so.1
librte_cryptodev.so.4
librte_distributor.so.1
librte_eal.so.6
include $(RTE_SDK)/mk/rte.vars.mk
+ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOOL),yy)
+DIRS-y += octeontx
+endif
+
include $(RTE_SDK)/mk/rte.subdir.mk
# Copyright(c) 2018 Cavium, Inc
std_deps = ['eal']
+drivers = ['octeontx']
config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
driver_name_fmt = 'rte_common_@0@'
--- /dev/null
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Cavium, Inc
+#
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+#
+# library name
+#
+LIB = librte_common_octeontx.a
+
+CFLAGS += $(WERROR_FLAGS)
+EXPORT_MAP := rte_common_octeontx_version.map
+
+LIBABIVER := 1
+
+#
+# all source are stored in SRCS-y
+#
+SRCS-y += octeontx_mbox.c
+
+LDLIBS += -lrte_eal
+
+include $(RTE_SDK)/mk/rte.lib.mk
--- /dev/null
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Cavium, Inc
+#
+
+sources = files('octeontx_mbox.c')
--- /dev/null
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#include <string.h>
+
+#include <rte_atomic.h>
+#include <rte_common.h>
+#include <rte_cycles.h>
+#include <rte_io.h>
+#include <rte_spinlock.h>
+
+#include "octeontx_mbox.h"
+
+/* Mbox operation timeout in seconds */
+#define MBOX_WAIT_TIME_SEC 3
+#define MAX_RAM_MBOX_LEN ((SSOW_BAR4_LEN >> 1) - 8 /* Mbox header */)
+
+/* Mbox channel state */
+enum {
+ MBOX_CHAN_STATE_REQ = 1,
+ MBOX_CHAN_STATE_RES = 0,
+};
+
+/* Response messages */
+enum {
+ MBOX_RET_SUCCESS,
+ MBOX_RET_INVALID,
+ MBOX_RET_INTERNAL_ERR,
+};
+
+struct mbox {
+ int init_once;
+ uint8_t *ram_mbox_base; /* Base address of mbox message stored in ram */
+ uint8_t *reg; /* Store to this register triggers PF mbox interrupt */
+ uint16_t tag_own; /* Last tag which was written to own channel */
+ rte_spinlock_t lock;
+};
+
+static struct mbox octeontx_mbox;
+
+/*
+ * Structure used for mbox synchronization
+ * This structure sits at the begin of Mbox RAM and used as main
+ * synchronization point for channel communication
+ */
+struct mbox_ram_hdr {
+ union {
+ uint64_t u64;
+ struct {
+ uint8_t chan_state : 1;
+ uint8_t coproc : 7;
+ uint8_t msg;
+ uint8_t vfid;
+ uint8_t res_code;
+ uint16_t tag;
+ uint16_t len;
+ };
+ };
+};
+
+int octeontx_logtype_mbox;
+
+RTE_INIT(otx_init_log);
+static void
+otx_init_log(void)
+{
+ octeontx_logtype_mbox = rte_log_register("pmd.octeontx.mbox");
+ if (octeontx_logtype_mbox >= 0)
+ rte_log_set_level(octeontx_logtype_mbox, RTE_LOG_NOTICE);
+}
+
+static inline void
+mbox_msgcpy(volatile uint8_t *d, volatile const uint8_t *s, uint16_t size)
+{
+ uint16_t i;
+
+ for (i = 0; i < size; i++)
+ d[i] = s[i];
+}
+
+static inline void
+mbox_send_request(struct mbox *m, struct octeontx_mbox_hdr *hdr,
+ const void *txmsg, uint16_t txsize)
+{
+ struct mbox_ram_hdr old_hdr;
+ struct mbox_ram_hdr new_hdr = { {0} };
+ uint64_t *ram_mbox_hdr = (uint64_t *)m->ram_mbox_base;
+ uint8_t *ram_mbox_msg = m->ram_mbox_base + sizeof(struct mbox_ram_hdr);
+
+ /*
+ * Initialize the channel with the tag left by last send.
+ * On success full mbox send complete, PF increments the tag by one.
+ * The sender can validate integrity of PF message with this scheme
+ */
+ old_hdr.u64 = rte_read64(ram_mbox_hdr);
+ m->tag_own = (old_hdr.tag + 2) & (~0x1ul); /* next even number */
+
+ /* Copy msg body */
+ if (txmsg)
+ mbox_msgcpy(ram_mbox_msg, txmsg, txsize);
+
+ /* Prepare new hdr */
+ new_hdr.chan_state = MBOX_CHAN_STATE_REQ;
+ new_hdr.coproc = hdr->coproc;
+ new_hdr.msg = hdr->msg;
+ new_hdr.vfid = hdr->vfid;
+ new_hdr.tag = m->tag_own;
+ new_hdr.len = txsize;
+
+ /* Write the msg header */
+ rte_write64(new_hdr.u64, ram_mbox_hdr);
+ rte_smp_wmb();
+ /* Notify PF about the new msg - write to MBOX reg generates PF IRQ */
+ rte_write64(0, m->reg);
+}
+
+static inline int
+mbox_wait_response(struct mbox *m, struct octeontx_mbox_hdr *hdr,
+ void *rxmsg, uint16_t rxsize)
+{
+ int res = 0, wait;
+ uint16_t len;
+ struct mbox_ram_hdr rx_hdr;
+ uint64_t *ram_mbox_hdr = (uint64_t *)m->ram_mbox_base;
+ uint8_t *ram_mbox_msg = m->ram_mbox_base + sizeof(struct mbox_ram_hdr);
+
+ /* Wait for response */
+ wait = MBOX_WAIT_TIME_SEC * 1000 * 10;
+ while (wait > 0) {
+ rte_delay_us(100);
+ rx_hdr.u64 = rte_read64(ram_mbox_hdr);
+ if (rx_hdr.chan_state == MBOX_CHAN_STATE_RES)
+ break;
+ --wait;
+ }
+
+ hdr->res_code = rx_hdr.res_code;
+ m->tag_own++;
+
+ /* Timeout */
+ if (wait <= 0) {
+ res = -ETIMEDOUT;
+ goto error;
+ }
+
+ /* Tag mismatch */
+ if (m->tag_own != rx_hdr.tag) {
+ res = -EINVAL;
+ goto error;
+ }
+
+ /* PF nacked the msg */
+ if (rx_hdr.res_code != MBOX_RET_SUCCESS) {
+ res = -EBADMSG;
+ goto error;
+ }
+
+ len = RTE_MIN(rx_hdr.len, rxsize);
+ if (rxmsg)
+ mbox_msgcpy(rxmsg, ram_mbox_msg, len);
+
+ return len;
+
+error:
+ mbox_log_err("Failed to send mbox(%d/%d) coproc=%d msg=%d ret=(%d,%d)",
+ m->tag_own, rx_hdr.tag, hdr->coproc, hdr->msg, res,
+ hdr->res_code);
+ return res;
+}
+
+static inline int
+mbox_send(struct mbox *m, struct octeontx_mbox_hdr *hdr, const void *txmsg,
+ uint16_t txsize, void *rxmsg, uint16_t rxsize)
+{
+ int res = -EINVAL;
+
+ if (m->init_once == 0 || hdr == NULL ||
+ txsize > MAX_RAM_MBOX_LEN || rxsize > MAX_RAM_MBOX_LEN) {
+ mbox_log_err("Invalid init_once=%d hdr=%p txsz=%d rxsz=%d",
+ m->init_once, hdr, txsize, rxsize);
+ return res;
+ }
+
+ rte_spinlock_lock(&m->lock);
+
+ mbox_send_request(m, hdr, txmsg, txsize);
+ res = mbox_wait_response(m, hdr, rxmsg, rxsize);
+
+ rte_spinlock_unlock(&m->lock);
+ return res;
+}
+
+int
+octeontx_mbox_set_ram_mbox_base(uint8_t *ram_mbox_base)
+{
+ struct mbox *m = &octeontx_mbox;
+
+ if (m->init_once)
+ return -EALREADY;
+
+ if (ram_mbox_base == NULL) {
+ mbox_log_err("Invalid ram_mbox_base=%p", ram_mbox_base);
+ return -EINVAL;
+ }
+
+ m->ram_mbox_base = ram_mbox_base;
+
+ if (m->reg != NULL) {
+ rte_spinlock_init(&m->lock);
+ m->init_once = 1;
+ }
+
+ return 0;
+}
+
+int
+octeontx_mbox_set_reg(uint8_t *reg)
+{
+ struct mbox *m = &octeontx_mbox;
+
+ if (m->init_once)
+ return -EALREADY;
+
+ if (reg == NULL) {
+ mbox_log_err("Invalid reg=%p", reg);
+ return -EINVAL;
+ }
+
+ m->reg = reg;
+
+ if (m->ram_mbox_base != NULL) {
+ rte_spinlock_init(&m->lock);
+ m->init_once = 1;
+ }
+
+ return 0;
+}
+
+int
+octeontx_mbox_send(struct octeontx_mbox_hdr *hdr, void *txdata,
+ uint16_t txlen, void *rxdata, uint16_t rxlen)
+{
+ struct mbox *m = &octeontx_mbox;
+
+ RTE_BUILD_BUG_ON(sizeof(struct mbox_ram_hdr) != 8);
+ if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+ return -EINVAL;
+
+ return mbox_send(m, hdr, txdata, txlen, rxdata, rxlen);
+}
--- /dev/null
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#ifndef __OCTEONTX_MBOX_H__
+#define __OCTEONTX_MBOX_H__
+
+#include <rte_common.h>
+#include <rte_spinlock.h>
+
+#define SSOW_BAR4_LEN (64 * 1024)
+#define SSO_VHGRP_PF_MBOX(x) (0x200ULL | ((x) << 3))
+
+#define MBOX_LOG(level, fmt, args...) \
+ rte_log(RTE_LOG_ ## level, octeontx_logtype_mbox,\
+ "%s() line %u: " fmt "\n", __func__, __LINE__, ## args)
+
+#define mbox_log_info(fmt, ...) MBOX_LOG(INFO, fmt, ##__VA_ARGS__)
+#define mbox_log_dbg(fmt, ...) MBOX_LOG(DEBUG, fmt, ##__VA_ARGS__)
+#define mbox_log_err(fmt, ...) MBOX_LOG(ERR, fmt, ##__VA_ARGS__)
+#define mbox_func_trace mbox_log_dbg
+
+extern int octeontx_logtype_mbox;
+
+struct octeontx_mbox_hdr {
+ uint16_t vfid; /* VF index or pf resource index local to the domain */
+ uint8_t coproc; /* Coprocessor id */
+ uint8_t msg; /* Message id */
+ uint8_t res_code; /* Functional layer response code */
+};
+
+int octeontx_mbox_set_ram_mbox_base(uint8_t *ram_mbox_base);
+int octeontx_mbox_set_reg(uint8_t *reg);
+int octeontx_mbox_send(struct octeontx_mbox_hdr *hdr,
+ void *txdata, uint16_t txlen, void *rxdata, uint16_t rxlen);
+
+#endif /* __OCTEONTX_MBOX_H__ */
--- /dev/null
+DPDK_18.05 {
+ global:
+
+ octeontx_mbox_set_ram_mbox_base;
+ octeontx_mbox_set_reg;
+ octeontx_mbox_send;
+};
LIB = librte_pmd_octeontx_ssovf.a
CFLAGS += $(WERROR_FLAGS)
+CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx/
CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx/
CFLAGS += -I$(RTE_SDK)/drivers/net/octeontx/
-LDLIBS += -lrte_eal -lrte_eventdev -lrte_mempool_octeontx -lrte_pmd_octeontx
+LDLIBS += -lrte_eal -lrte_eventdev -lrte_common_octeontx -lrte_pmd_octeontx
LDLIBS += -lrte_bus_pci -lrte_mempool -lrte_mbuf -lrte_kvargs
LDLIBS += -lrte_bus_vdev
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF) += ssovf_worker.c
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF) += ssovf_evdev.c
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF) += ssovf_evdev_selftest.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF) += ssovf_probe.c
ifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y)
CFLAGS_ssovf_worker.o += -fno-prefetch-loop-arrays
sources = files('ssovf_worker.c',
'ssovf_evdev.c',
- 'ssovf_evdev_selftest.c'
+ 'ssovf_evdev_selftest.c',
+ 'ssovf_probe.c'
)
-deps += ['mempool_octeontx', 'bus_vdev', 'pmd_octeontx']
+deps += ['common_octeontx', 'mempool_octeontx', 'bus_vdev', 'pmd_octeontx']
hdr.vfid = 0;
memset(info, 0, len);
- return octeontx_ssovf_mbox_send(&hdr, NULL, 0, info, len);
+ return octeontx_mbox_send(&hdr, NULL, 0, info, len);
}
struct ssovf_mbox_getwork_wait {
hdr.vfid = 0;
tmo_set.wait_ns = timeout_ns;
- ret = octeontx_ssovf_mbox_send(&hdr, &tmo_set, len, NULL, 0);
+ ret = octeontx_mbox_send(&hdr, &tmo_set, len, NULL, 0);
if (ret)
ssovf_log_err("Failed to set getwork timeout(%d)", ret);
grp.affinity = 0xff;
grp.priority = prio / 32; /* Normalize to 0 to 7 */
- ret = octeontx_ssovf_mbox_send(&hdr, &grp, len, NULL, 0);
+ ret = octeontx_mbox_send(&hdr, &grp, len, NULL, 0);
if (ret)
ssovf_log_err("Failed to set grp=%d prio=%d", queue, prio);
memset(&ns2iter, 0, len);
ns2iter.wait_ns = ns;
- ret = octeontx_ssovf_mbox_send(&hdr, &ns2iter, len, &ns2iter, len);
+ ret = octeontx_mbox_send(&hdr, &ns2iter, len, &ns2iter, len);
if (ret < 0 || (ret != len)) {
ssovf_log_err("Failed to get tmo ticks ns=%"PRId64"", ns);
return -EIO;
return -ENOMEM;
}
- ws->base = octeontx_ssovf_bar(OCTEONTX_SSO_HWS, port_id, 0);
+ ws->base = ssovf_bar(OCTEONTX_SSO_HWS, port_id, 0);
if (ws->base == NULL) {
rte_free(ws);
ssovf_log_err("Failed to get hws base addr port=%d", port_id);
ws->port = port_id;
for (q = 0; q < edev->nb_event_queues; q++) {
- ws->grps[q] = octeontx_ssovf_bar(OCTEONTX_SSO_GROUP, q, 2);
+ ws->grps[q] = ssovf_bar(OCTEONTX_SSO_GROUP, q, 2);
if (ws->grps[q] == NULL) {
rte_free(ws);
ssovf_log_err("Failed to get grp%d base addr", q);
/* Consume all the events through HWS0 */
ssows_flush_events(dev->data->ports[0], i);
- base = octeontx_ssovf_bar(OCTEONTX_SSO_GROUP, i, 0);
+ base = ssovf_bar(OCTEONTX_SSO_GROUP, i, 0);
base += SSO_VHGRP_QCTL;
ssovf_write64(1, base); /* Enable SSO group */
}
/* Consume all the events through HWS0 */
ssows_flush_events(dev->data->ports[0], i);
- base = octeontx_ssovf_bar(OCTEONTX_SSO_GROUP, i, 0);
+ base = ssovf_bar(OCTEONTX_SSO_GROUP, i, 0);
base += SSO_VHGRP_QCTL;
ssovf_write64(0, base); /* Disable SSO group */
}
static int
ssovf_vdev_probe(struct rte_vdev_device *vdev)
{
- struct octeontx_ssovf_info oinfo;
+ struct ssovf_info oinfo;
struct ssovf_mbox_dev_info info;
struct ssovf_evdev *edev;
struct rte_eventdev *eventdev;
return 0;
}
- ret = octeontx_ssovf_info(&oinfo);
+ ret = ssovf_info(&oinfo);
if (ret) {
ssovf_log_err("Failed to probe and validate ssovfs %d", ret);
goto error;
} while (0)
#endif
+struct ssovf_info {
+ uint16_t domain; /* Domain id */
+ uint8_t total_ssovfs; /* Total sso groups available in domain */
+ uint8_t total_ssowvfs;/* Total sso hws available in domain */
+};
+
+enum ssovf_type {
+ OCTEONTX_SSO_GROUP, /* SSO group vf */
+ OCTEONTX_SSO_HWS, /* SSO hardware workslot vf */
+};
struct ssovf_evdev {
uint8_t max_event_queues;
uint16_t nb_events, uint64_t timeout_ticks);
void ssows_flush_events(struct ssows *ws, uint8_t queue_id);
void ssows_reset(struct ssows *ws);
+int ssovf_info(struct ssovf_info *info);
+void *ssovf_bar(enum ssovf_type, uint8_t id, uint8_t bar);
int test_eventdev_octeontx(void);
#endif /* __SSOVF_EVDEV_H__ */
--- /dev/null
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#include <rte_atomic.h>
+#include <rte_common.h>
+#include <rte_eal.h>
+#include <rte_io.h>
+#include <rte_pci.h>
+#include <rte_bus_pci.h>
+
+#include "octeontx_mbox.h"
+#include "ssovf_evdev.h"
+
+#define PCI_VENDOR_ID_CAVIUM 0x177D
+#define PCI_DEVICE_ID_OCTEONTX_SSOGRP_VF 0xA04B
+#define PCI_DEVICE_ID_OCTEONTX_SSOWS_VF 0xA04D
+
+#define SSO_MAX_VHGRP (64)
+#define SSO_MAX_VHWS (32)
+
+#define SSO_VHGRP_AQ_THR (0x1E0ULL)
+
+struct ssovf_res {
+ uint16_t domain;
+ uint16_t vfid;
+ void *bar0;
+ void *bar2;
+};
+
+struct ssowvf_res {
+ uint16_t domain;
+ uint16_t vfid;
+ void *bar0;
+ void *bar2;
+ void *bar4;
+};
+
+struct ssowvf_identify {
+ uint16_t domain;
+ uint16_t vfid;
+};
+
+struct ssodev {
+ uint8_t total_ssovfs;
+ uint8_t total_ssowvfs;
+ struct ssovf_res grp[SSO_MAX_VHGRP];
+ struct ssowvf_res hws[SSO_MAX_VHWS];
+};
+
+static struct ssodev sdev;
+
+/* Interface functions */
+int
+ssovf_info(struct ssovf_info *info)
+{
+ uint8_t i;
+ uint16_t domain;
+
+ if (rte_eal_process_type() != RTE_PROC_PRIMARY || info == NULL)
+ return -EINVAL;
+
+ if (sdev.total_ssovfs == 0 || sdev.total_ssowvfs == 0)
+ return -ENODEV;
+
+ domain = sdev.grp[0].domain;
+ for (i = 0; i < sdev.total_ssovfs; i++) {
+ /* Check vfid's are contiguous and belong to same domain */
+ if (sdev.grp[i].vfid != i ||
+ sdev.grp[i].bar0 == NULL ||
+ sdev.grp[i].domain != domain) {
+ mbox_log_err("GRP error, vfid=%d/%d domain=%d/%d %p",
+ i, sdev.grp[i].vfid,
+ domain, sdev.grp[i].domain,
+ sdev.grp[i].bar0);
+ return -EINVAL;
+ }
+ }
+
+ for (i = 0; i < sdev.total_ssowvfs; i++) {
+ /* Check vfid's are contiguous and belong to same domain */
+ if (sdev.hws[i].vfid != i ||
+ sdev.hws[i].bar0 == NULL ||
+ sdev.hws[i].domain != domain) {
+ mbox_log_err("HWS error, vfid=%d/%d domain=%d/%d %p",
+ i, sdev.hws[i].vfid,
+ domain, sdev.hws[i].domain,
+ sdev.hws[i].bar0);
+ return -EINVAL;
+ }
+ }
+
+ info->domain = domain;
+ info->total_ssovfs = sdev.total_ssovfs;
+ info->total_ssowvfs = sdev.total_ssowvfs;
+ return 0;
+}
+
+void*
+ssovf_bar(enum ssovf_type type, uint8_t id, uint8_t bar)
+{
+ if (rte_eal_process_type() != RTE_PROC_PRIMARY ||
+ type > OCTEONTX_SSO_HWS)
+ return NULL;
+
+ if (type == OCTEONTX_SSO_GROUP) {
+ if (id >= sdev.total_ssovfs)
+ return NULL;
+ } else {
+ if (id >= sdev.total_ssowvfs)
+ return NULL;
+ }
+
+ if (type == OCTEONTX_SSO_GROUP) {
+ switch (bar) {
+ case 0:
+ return sdev.grp[id].bar0;
+ case 2:
+ return sdev.grp[id].bar2;
+ default:
+ return NULL;
+ }
+ } else {
+ switch (bar) {
+ case 0:
+ return sdev.hws[id].bar0;
+ case 2:
+ return sdev.hws[id].bar2;
+ case 4:
+ return sdev.hws[id].bar4;
+ default:
+ return NULL;
+ }
+ }
+}
+
+/* SSOWVF pcie device aka event port probe */
+
+static int
+ssowvf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
+{
+ uint16_t vfid;
+ struct ssowvf_res *res;
+ struct ssowvf_identify *id;
+ uint8_t *ram_mbox_base;
+
+ RTE_SET_USED(pci_drv);
+
+ /* For secondary processes, the primary has done all the work */
+ if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+ return 0;
+
+ if (pci_dev->mem_resource[0].addr == NULL ||
+ pci_dev->mem_resource[2].addr == NULL ||
+ pci_dev->mem_resource[4].addr == NULL) {
+ mbox_log_err("Empty bars %p %p %p",
+ pci_dev->mem_resource[0].addr,
+ pci_dev->mem_resource[2].addr,
+ pci_dev->mem_resource[4].addr);
+ return -ENODEV;
+ }
+
+ if (pci_dev->mem_resource[4].len != SSOW_BAR4_LEN) {
+ mbox_log_err("Bar4 len mismatch %d != %d",
+ SSOW_BAR4_LEN, (int)pci_dev->mem_resource[4].len);
+ return -EINVAL;
+ }
+
+ id = pci_dev->mem_resource[4].addr;
+ vfid = id->vfid;
+ if (vfid >= SSO_MAX_VHWS) {
+ mbox_log_err("Invalid vfid(%d/%d)", vfid, SSO_MAX_VHWS);
+ return -EINVAL;
+ }
+
+ res = &sdev.hws[vfid];
+ res->vfid = vfid;
+ res->bar0 = pci_dev->mem_resource[0].addr;
+ res->bar2 = pci_dev->mem_resource[2].addr;
+ res->bar4 = pci_dev->mem_resource[4].addr;
+ res->domain = id->domain;
+
+ sdev.total_ssowvfs++;
+ if (vfid == 0) {
+ ram_mbox_base = ssovf_bar(OCTEONTX_SSO_HWS, 0, 4);
+ if (octeontx_mbox_set_ram_mbox_base(ram_mbox_base)) {
+ mbox_log_err("Invalid Failed to set ram mbox base");
+ return -EINVAL;
+ }
+ }
+
+ rte_wmb();
+ mbox_log_dbg("Domain=%d hws=%d total_ssowvfs=%d", res->domain,
+ res->vfid, sdev.total_ssowvfs);
+ return 0;
+}
+
+static const struct rte_pci_id pci_ssowvf_map[] = {
+ {
+ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
+ PCI_DEVICE_ID_OCTEONTX_SSOWS_VF)
+ },
+ {
+ .vendor_id = 0,
+ },
+};
+
+static struct rte_pci_driver pci_ssowvf = {
+ .id_table = pci_ssowvf_map,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
+ .probe = ssowvf_probe,
+};
+
+RTE_PMD_REGISTER_PCI(octeontx_ssowvf, pci_ssowvf);
+
+/* SSOVF pcie device aka event queue probe */
+
+static int
+ssovf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
+{
+ uint64_t val;
+ uint16_t vfid;
+ uint8_t *idreg;
+ struct ssovf_res *res;
+ uint8_t *reg;
+
+ RTE_SET_USED(pci_drv);
+
+ /* For secondary processes, the primary has done all the work */
+ if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+ return 0;
+
+ if (pci_dev->mem_resource[0].addr == NULL ||
+ pci_dev->mem_resource[2].addr == NULL) {
+ mbox_log_err("Empty bars %p %p",
+ pci_dev->mem_resource[0].addr,
+ pci_dev->mem_resource[2].addr);
+ return -ENODEV;
+ }
+ idreg = pci_dev->mem_resource[0].addr;
+ idreg += SSO_VHGRP_AQ_THR;
+ val = rte_read64(idreg);
+
+ /* Write back the default value of aq_thr */
+ rte_write64((1ULL << 33) - 1, idreg);
+ vfid = (val >> 16) & 0xffff;
+ if (vfid >= SSO_MAX_VHGRP) {
+ mbox_log_err("Invalid vfid (%d/%d)", vfid, SSO_MAX_VHGRP);
+ return -EINVAL;
+ }
+
+ res = &sdev.grp[vfid];
+ res->vfid = vfid;
+ res->bar0 = pci_dev->mem_resource[0].addr;
+ res->bar2 = pci_dev->mem_resource[2].addr;
+ res->domain = val & 0xffff;
+
+ sdev.total_ssovfs++;
+ if (vfid == 0) {
+ reg = ssovf_bar(OCTEONTX_SSO_GROUP, 0, 0);
+ reg += SSO_VHGRP_PF_MBOX(1);
+ if (octeontx_mbox_set_reg(reg)) {
+ mbox_log_err("Invalid Failed to set mbox_reg");
+ return -EINVAL;
+ }
+ }
+
+ rte_wmb();
+ mbox_log_dbg("Domain=%d group=%d total_ssovfs=%d", res->domain,
+ res->vfid, sdev.total_ssovfs);
+ return 0;
+}
+
+static const struct rte_pci_id pci_ssovf_map[] = {
+ {
+ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
+ PCI_DEVICE_ID_OCTEONTX_SSOGRP_VF)
+ },
+ {
+ .vendor_id = 0,
+ },
+};
+
+static struct rte_pci_driver pci_ssovf = {
+ .id_table = pci_ssovf_map,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
+ .probe = ssovf_probe,
+};
+
+RTE_PMD_REGISTER_PCI(octeontx_ssovf, pci_ssovf);
uint64_t aq_cnt = 1;
uint64_t cq_ds_cnt = 1;
uint64_t enable, get_work0, get_work1;
- uint8_t *base = octeontx_ssovf_bar(OCTEONTX_SSO_GROUP, queue_id, 0);
+ uint8_t *base = ssovf_bar(OCTEONTX_SSO_GROUP, queue_id, 0);
enable = ssovf_read64(base + SSO_VHGRP_QCTL);
if (!enable)
LIB = librte_mempool_octeontx.a
CFLAGS += $(WERROR_FLAGS)
+CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx/
EXPORT_MAP := rte_mempool_octeontx_version.map
LIBABIVER := 1
#
# all source are stored in SRCS-y
#
-SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOOL) += octeontx_ssovf.c
-SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOOL) += octeontx_mbox.c
SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOOL) += octeontx_fpavf.c
SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOOL) += rte_mempool_octeontx.c
endif
LDLIBS += -lrte_eal -lrte_mempool -lrte_ring -lrte_mbuf
-LDLIBS += -lrte_bus_pci
+LDLIBS += -lrte_bus_pci -lrte_common_octeontx
include $(RTE_SDK)/mk/rte.lib.mk
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Cavium, Inc
-sources = files('octeontx_ssovf.c',
- 'octeontx_mbox.c',
- 'octeontx_fpavf.c',
+sources = files('octeontx_fpavf.c',
'rte_mempool_octeontx.c'
)
-deps += ['mbuf', 'bus_pci']
+deps += ['mbuf', 'bus_pci', 'common_octeontx']
octeontx_logtype_fpavf = rte_log_register("pmd.mempool.octeontx");
if (octeontx_logtype_fpavf >= 0)
rte_log_set_level(octeontx_logtype_fpavf, RTE_LOG_NOTICE);
-
- octeontx_logtype_fpavf_mbox = rte_log_register("pmd.mempool.octeontx.mbox");
- if (octeontx_logtype_fpavf_mbox >= 0)
- rte_log_set_level(octeontx_logtype_fpavf_mbox, RTE_LOG_NOTICE);
}
/* lock is taken by caller */
cfg.pool_stack_end = phys_addr + memsz;
cfg.aura_cfg = (1 << 9);
- ret = octeontx_ssovf_mbox_send(&hdr, &cfg,
+ ret = octeontx_mbox_send(&hdr, &cfg,
sizeof(struct octeontx_mbox_fpa_cfg),
&resp, sizeof(resp));
if (ret < 0) {
cfg.pool_stack_end = 0;
cfg.aura_cfg = 0;
- ret = octeontx_ssovf_mbox_send(&hdr, &cfg,
+ ret = octeontx_mbox_send(&hdr, &cfg,
sizeof(struct octeontx_mbox_fpa_cfg),
&resp, sizeof(resp));
if (ret < 0) {
memset(&cfg, 0x0, sizeof(struct octeontx_mbox_fpa_cfg));
cfg.aid = gpool_index; /* gpool is guara */
- ret = octeontx_ssovf_mbox_send(&hdr, &cfg,
+ ret = octeontx_mbox_send(&hdr, &cfg,
sizeof(struct octeontx_mbox_fpa_cfg),
&resp, sizeof(resp));
if (ret < 0) {
hdr.coproc = FPA_COPROC;
hdr.msg = FPA_DETACHAURA;
hdr.vfid = gpool_index;
- ret = octeontx_ssovf_mbox_send(&hdr, &cfg, sizeof(cfg), NULL, 0);
+ ret = octeontx_mbox_send(&hdr, &cfg, sizeof(cfg), NULL, 0);
if (ret < 0) {
fpavf_log_err("Couldn't detach FPA aura %d Err=%d FuncErr=%d\n",
gpool_index, ret, hdr.res_code);
hdr.coproc = FPA_COPROC;
hdr.msg = FPA_START_COUNT;
hdr.vfid = gpool_index;
- ret = octeontx_ssovf_mbox_send(&hdr, NULL, 0, NULL, 0);
+ ret = octeontx_mbox_send(&hdr, NULL, 0, NULL, 0);
if (ret < 0) {
fpavf_log_err("Could not start buffer counting for ");
fpavf_log_err("FPA pool %d. Err=%d. FuncErr=%d\n",
+++ /dev/null
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2017 Cavium, Inc
- */
-
-#include <string.h>
-
-#include <rte_atomic.h>
-#include <rte_common.h>
-#include <rte_cycles.h>
-#include <rte_io.h>
-#include <rte_spinlock.h>
-
-#include "octeontx_mbox.h"
-#include "octeontx_pool_logs.h"
-
-/* Mbox operation timeout in seconds */
-#define MBOX_WAIT_TIME_SEC 3
-#define MAX_RAM_MBOX_LEN ((SSOW_BAR4_LEN >> 1) - 8 /* Mbox header */)
-
-/* Mbox channel state */
-enum {
- MBOX_CHAN_STATE_REQ = 1,
- MBOX_CHAN_STATE_RES = 0,
-};
-
-/* Response messages */
-enum {
- MBOX_RET_SUCCESS,
- MBOX_RET_INVALID,
- MBOX_RET_INTERNAL_ERR,
-};
-
-struct mbox {
- int init_once;
- uint8_t *ram_mbox_base; /* Base address of mbox message stored in ram */
- uint8_t *reg; /* Store to this register triggers PF mbox interrupt */
- uint16_t tag_own; /* Last tag which was written to own channel */
- rte_spinlock_t lock;
-};
-
-static struct mbox octeontx_mbox;
-
-/*
- * Structure used for mbox synchronization
- * This structure sits at the begin of Mbox RAM and used as main
- * synchronization point for channel communication
- */
-struct mbox_ram_hdr {
- union {
- uint64_t u64;
- struct {
- uint8_t chan_state : 1;
- uint8_t coproc : 7;
- uint8_t msg;
- uint8_t vfid;
- uint8_t res_code;
- uint16_t tag;
- uint16_t len;
- };
- };
-};
-
-static inline void
-mbox_msgcpy(volatile uint8_t *d, volatile const uint8_t *s, uint16_t size)
-{
- uint16_t i;
-
- for (i = 0; i < size; i++)
- d[i] = s[i];
-}
-
-static inline void
-mbox_send_request(struct mbox *m, struct octeontx_mbox_hdr *hdr,
- const void *txmsg, uint16_t txsize)
-{
- struct mbox_ram_hdr old_hdr;
- struct mbox_ram_hdr new_hdr = { {0} };
- uint64_t *ram_mbox_hdr = (uint64_t *)m->ram_mbox_base;
- uint8_t *ram_mbox_msg = m->ram_mbox_base + sizeof(struct mbox_ram_hdr);
-
- /*
- * Initialize the channel with the tag left by last send.
- * On success full mbox send complete, PF increments the tag by one.
- * The sender can validate integrity of PF message with this scheme
- */
- old_hdr.u64 = rte_read64(ram_mbox_hdr);
- m->tag_own = (old_hdr.tag + 2) & (~0x1ul); /* next even number */
-
- /* Copy msg body */
- if (txmsg)
- mbox_msgcpy(ram_mbox_msg, txmsg, txsize);
-
- /* Prepare new hdr */
- new_hdr.chan_state = MBOX_CHAN_STATE_REQ;
- new_hdr.coproc = hdr->coproc;
- new_hdr.msg = hdr->msg;
- new_hdr.vfid = hdr->vfid;
- new_hdr.tag = m->tag_own;
- new_hdr.len = txsize;
-
- /* Write the msg header */
- rte_write64(new_hdr.u64, ram_mbox_hdr);
- rte_smp_wmb();
- /* Notify PF about the new msg - write to MBOX reg generates PF IRQ */
- rte_write64(0, m->reg);
-}
-
-static inline int
-mbox_wait_response(struct mbox *m, struct octeontx_mbox_hdr *hdr,
- void *rxmsg, uint16_t rxsize)
-{
- int res = 0, wait;
- uint16_t len;
- struct mbox_ram_hdr rx_hdr;
- uint64_t *ram_mbox_hdr = (uint64_t *)m->ram_mbox_base;
- uint8_t *ram_mbox_msg = m->ram_mbox_base + sizeof(struct mbox_ram_hdr);
-
- /* Wait for response */
- wait = MBOX_WAIT_TIME_SEC * 1000 * 10;
- while (wait > 0) {
- rte_delay_us(100);
- rx_hdr.u64 = rte_read64(ram_mbox_hdr);
- if (rx_hdr.chan_state == MBOX_CHAN_STATE_RES)
- break;
- --wait;
- }
-
- hdr->res_code = rx_hdr.res_code;
- m->tag_own++;
-
- /* Timeout */
- if (wait <= 0) {
- res = -ETIMEDOUT;
- goto error;
- }
-
- /* Tag mismatch */
- if (m->tag_own != rx_hdr.tag) {
- res = -EINVAL;
- goto error;
- }
-
- /* PF nacked the msg */
- if (rx_hdr.res_code != MBOX_RET_SUCCESS) {
- res = -EBADMSG;
- goto error;
- }
-
- len = RTE_MIN(rx_hdr.len, rxsize);
- if (rxmsg)
- mbox_msgcpy(rxmsg, ram_mbox_msg, len);
-
- return len;
-
-error:
- mbox_log_err("Failed to send mbox(%d/%d) coproc=%d msg=%d ret=(%d,%d)",
- m->tag_own, rx_hdr.tag, hdr->coproc, hdr->msg, res,
- hdr->res_code);
- return res;
-}
-
-static inline int
-mbox_send(struct mbox *m, struct octeontx_mbox_hdr *hdr, const void *txmsg,
- uint16_t txsize, void *rxmsg, uint16_t rxsize)
-{
- int res = -EINVAL;
-
- if (m->init_once == 0 || hdr == NULL ||
- txsize > MAX_RAM_MBOX_LEN || rxsize > MAX_RAM_MBOX_LEN) {
- mbox_log_err("Invalid init_once=%d hdr=%p txsz=%d rxsz=%d",
- m->init_once, hdr, txsize, rxsize);
- return res;
- }
-
- rte_spinlock_lock(&m->lock);
-
- mbox_send_request(m, hdr, txmsg, txsize);
- res = mbox_wait_response(m, hdr, rxmsg, rxsize);
-
- rte_spinlock_unlock(&m->lock);
- return res;
-}
-
-static inline int
-mbox_setup(struct mbox *m)
-{
- if (unlikely(m->init_once == 0)) {
- rte_spinlock_init(&m->lock);
- m->ram_mbox_base = octeontx_ssovf_bar(OCTEONTX_SSO_HWS, 0, 4);
- m->reg = octeontx_ssovf_bar(OCTEONTX_SSO_GROUP, 0, 0);
- m->reg += SSO_VHGRP_PF_MBOX(1);
-
- if (m->ram_mbox_base == NULL || m->reg == NULL) {
- mbox_log_err("Invalid ram_mbox_base=%p or reg=%p",
- m->ram_mbox_base, m->reg);
- return -EINVAL;
- }
- m->init_once = 1;
- }
- return 0;
-}
-
-int
-octeontx_ssovf_mbox_send(struct octeontx_mbox_hdr *hdr, void *txdata,
- uint16_t txlen, void *rxdata, uint16_t rxlen)
-{
- struct mbox *m = &octeontx_mbox;
-
- RTE_BUILD_BUG_ON(sizeof(struct mbox_ram_hdr) != 8);
- if (rte_eal_process_type() != RTE_PROC_PRIMARY || mbox_setup(m))
- return -EINVAL;
-
- return mbox_send(m, hdr, txdata, txlen, rxdata, rxlen);
-}
+++ /dev/null
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2017 Cavium, Inc
- */
-
-#ifndef __OCTEONTX_MBOX_H__
-#define __OCTEONTX_MBOX_H__
-
-#include <rte_common.h>
-
-#define SSOW_BAR4_LEN (64 * 1024)
-#define SSO_VHGRP_PF_MBOX(x) (0x200ULL | ((x) << 3))
-
-struct octeontx_ssovf_info {
- uint16_t domain; /* Domain id */
- uint8_t total_ssovfs; /* Total sso groups available in domain */
- uint8_t total_ssowvfs;/* Total sso hws available in domain */
-};
-
-enum octeontx_ssovf_type {
- OCTEONTX_SSO_GROUP, /* SSO group vf */
- OCTEONTX_SSO_HWS, /* SSO hardware workslot vf */
-};
-
-struct octeontx_mbox_hdr {
- uint16_t vfid; /* VF index or pf resource index local to the domain */
- uint8_t coproc; /* Coprocessor id */
- uint8_t msg; /* Message id */
- uint8_t res_code; /* Functional layer response code */
-};
-
-int octeontx_ssovf_info(struct octeontx_ssovf_info *info);
-void *octeontx_ssovf_bar(enum octeontx_ssovf_type, uint8_t id, uint8_t bar);
-int octeontx_ssovf_mbox_send(struct octeontx_mbox_hdr *hdr,
- void *txdata, uint16_t txlen, void *rxdata, uint16_t rxlen);
-
-#endif /* __OCTEONTX_MBOX_H__ */
rte_log(RTE_LOG_ ## level, octeontx_logtype_fpavf,\
"%s() line %u: " fmt "\n", __func__, __LINE__, ## args)
-#define MBOX_LOG(level, fmt, args...) \
- rte_log(RTE_LOG_ ## level, octeontx_logtype_fpavf_mbox,\
- "%s() line %u: " fmt "\n", __func__, __LINE__, ## args)
-
#define fpavf_log_info(fmt, ...) FPAVF_LOG(INFO, fmt, ##__VA_ARGS__)
#define fpavf_log_dbg(fmt, ...) FPAVF_LOG(DEBUG, fmt, ##__VA_ARGS__)
#define fpavf_log_err(fmt, ...) FPAVF_LOG(ERR, fmt, ##__VA_ARGS__)
#define fpavf_func_trace fpavf_log_dbg
-#define mbox_log_info(fmt, ...) MBOX_LOG(INFO, fmt, ##__VA_ARGS__)
-#define mbox_log_dbg(fmt, ...) MBOX_LOG(DEBUG, fmt, ##__VA_ARGS__)
-#define mbox_log_err(fmt, ...) MBOX_LOG(ERR, fmt, ##__VA_ARGS__)
-#define mbox_func_trace mbox_log_dbg
extern int octeontx_logtype_fpavf;
-extern int octeontx_logtype_fpavf_mbox;
#endif /* __OCTEONTX_POOL_LOGS_H__*/
+++ /dev/null
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2017 Cavium, Inc
- */
-
-#include <rte_atomic.h>
-#include <rte_common.h>
-#include <rte_eal.h>
-#include <rte_io.h>
-#include <rte_pci.h>
-#include <rte_bus_pci.h>
-
-#include "octeontx_mbox.h"
-#include "octeontx_pool_logs.h"
-
-#define PCI_VENDOR_ID_CAVIUM 0x177D
-#define PCI_DEVICE_ID_OCTEONTX_SSOGRP_VF 0xA04B
-#define PCI_DEVICE_ID_OCTEONTX_SSOWS_VF 0xA04D
-
-#define SSO_MAX_VHGRP (64)
-#define SSO_MAX_VHWS (32)
-
-#define SSO_VHGRP_AQ_THR (0x1E0ULL)
-
-struct ssovf_res {
- uint16_t domain;
- uint16_t vfid;
- void *bar0;
- void *bar2;
-};
-
-struct ssowvf_res {
- uint16_t domain;
- uint16_t vfid;
- void *bar0;
- void *bar2;
- void *bar4;
-};
-
-struct ssowvf_identify {
- uint16_t domain;
- uint16_t vfid;
-};
-
-struct ssodev {
- uint8_t total_ssovfs;
- uint8_t total_ssowvfs;
- struct ssovf_res grp[SSO_MAX_VHGRP];
- struct ssowvf_res hws[SSO_MAX_VHWS];
-};
-
-static struct ssodev sdev;
-
-/* Interface functions */
-int
-octeontx_ssovf_info(struct octeontx_ssovf_info *info)
-{
- uint8_t i;
- uint16_t domain;
-
- if (rte_eal_process_type() != RTE_PROC_PRIMARY || info == NULL)
- return -EINVAL;
-
- if (sdev.total_ssovfs == 0 || sdev.total_ssowvfs == 0)
- return -ENODEV;
-
- domain = sdev.grp[0].domain;
- for (i = 0; i < sdev.total_ssovfs; i++) {
- /* Check vfid's are contiguous and belong to same domain */
- if (sdev.grp[i].vfid != i ||
- sdev.grp[i].bar0 == NULL ||
- sdev.grp[i].domain != domain) {
- mbox_log_err("GRP error, vfid=%d/%d domain=%d/%d %p",
- i, sdev.grp[i].vfid,
- domain, sdev.grp[i].domain,
- sdev.grp[i].bar0);
- return -EINVAL;
- }
- }
-
- for (i = 0; i < sdev.total_ssowvfs; i++) {
- /* Check vfid's are contiguous and belong to same domain */
- if (sdev.hws[i].vfid != i ||
- sdev.hws[i].bar0 == NULL ||
- sdev.hws[i].domain != domain) {
- mbox_log_err("HWS error, vfid=%d/%d domain=%d/%d %p",
- i, sdev.hws[i].vfid,
- domain, sdev.hws[i].domain,
- sdev.hws[i].bar0);
- return -EINVAL;
- }
- }
-
- info->domain = domain;
- info->total_ssovfs = sdev.total_ssovfs;
- info->total_ssowvfs = sdev.total_ssowvfs;
- return 0;
-}
-
-void*
-octeontx_ssovf_bar(enum octeontx_ssovf_type type, uint8_t id, uint8_t bar)
-{
- if (rte_eal_process_type() != RTE_PROC_PRIMARY ||
- type > OCTEONTX_SSO_HWS)
- return NULL;
-
- if (type == OCTEONTX_SSO_GROUP) {
- if (id >= sdev.total_ssovfs)
- return NULL;
- } else {
- if (id >= sdev.total_ssowvfs)
- return NULL;
- }
-
- if (type == OCTEONTX_SSO_GROUP) {
- switch (bar) {
- case 0:
- return sdev.grp[id].bar0;
- case 2:
- return sdev.grp[id].bar2;
- default:
- return NULL;
- }
- } else {
- switch (bar) {
- case 0:
- return sdev.hws[id].bar0;
- case 2:
- return sdev.hws[id].bar2;
- case 4:
- return sdev.hws[id].bar4;
- default:
- return NULL;
- }
- }
-}
-
-/* SSOWVF pcie device aka event port probe */
-
-static int
-ssowvf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
-{
- uint16_t vfid;
- struct ssowvf_res *res;
- struct ssowvf_identify *id;
-
- RTE_SET_USED(pci_drv);
-
- /* For secondary processes, the primary has done all the work */
- if (rte_eal_process_type() != RTE_PROC_PRIMARY)
- return 0;
-
- if (pci_dev->mem_resource[0].addr == NULL ||
- pci_dev->mem_resource[2].addr == NULL ||
- pci_dev->mem_resource[4].addr == NULL) {
- mbox_log_err("Empty bars %p %p %p",
- pci_dev->mem_resource[0].addr,
- pci_dev->mem_resource[2].addr,
- pci_dev->mem_resource[4].addr);
- return -ENODEV;
- }
-
- if (pci_dev->mem_resource[4].len != SSOW_BAR4_LEN) {
- mbox_log_err("Bar4 len mismatch %d != %d",
- SSOW_BAR4_LEN, (int)pci_dev->mem_resource[4].len);
- return -EINVAL;
- }
-
- id = pci_dev->mem_resource[4].addr;
- vfid = id->vfid;
- if (vfid >= SSO_MAX_VHWS) {
- mbox_log_err("Invalid vfid(%d/%d)", vfid, SSO_MAX_VHWS);
- return -EINVAL;
- }
-
- res = &sdev.hws[vfid];
- res->vfid = vfid;
- res->bar0 = pci_dev->mem_resource[0].addr;
- res->bar2 = pci_dev->mem_resource[2].addr;
- res->bar4 = pci_dev->mem_resource[4].addr;
- res->domain = id->domain;
-
- sdev.total_ssowvfs++;
- rte_wmb();
- mbox_log_dbg("Domain=%d hws=%d total_ssowvfs=%d", res->domain,
- res->vfid, sdev.total_ssowvfs);
- return 0;
-}
-
-static const struct rte_pci_id pci_ssowvf_map[] = {
- {
- RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
- PCI_DEVICE_ID_OCTEONTX_SSOWS_VF)
- },
- {
- .vendor_id = 0,
- },
-};
-
-static struct rte_pci_driver pci_ssowvf = {
- .id_table = pci_ssowvf_map,
- .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
- .probe = ssowvf_probe,
-};
-
-RTE_PMD_REGISTER_PCI(octeontx_ssowvf, pci_ssowvf);
-
-/* SSOVF pcie device aka event queue probe */
-
-static int
-ssovf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
-{
- uint64_t val;
- uint16_t vfid;
- uint8_t *idreg;
- struct ssovf_res *res;
-
- RTE_SET_USED(pci_drv);
-
- /* For secondary processes, the primary has done all the work */
- if (rte_eal_process_type() != RTE_PROC_PRIMARY)
- return 0;
-
- if (pci_dev->mem_resource[0].addr == NULL ||
- pci_dev->mem_resource[2].addr == NULL) {
- mbox_log_err("Empty bars %p %p",
- pci_dev->mem_resource[0].addr,
- pci_dev->mem_resource[2].addr);
- return -ENODEV;
- }
- idreg = pci_dev->mem_resource[0].addr;
- idreg += SSO_VHGRP_AQ_THR;
- val = rte_read64(idreg);
-
- /* Write back the default value of aq_thr */
- rte_write64((1ULL << 33) - 1, idreg);
- vfid = (val >> 16) & 0xffff;
- if (vfid >= SSO_MAX_VHGRP) {
- mbox_log_err("Invalid vfid (%d/%d)", vfid, SSO_MAX_VHGRP);
- return -EINVAL;
- }
-
- res = &sdev.grp[vfid];
- res->vfid = vfid;
- res->bar0 = pci_dev->mem_resource[0].addr;
- res->bar2 = pci_dev->mem_resource[2].addr;
- res->domain = val & 0xffff;
-
- sdev.total_ssovfs++;
- rte_wmb();
- mbox_log_dbg("Domain=%d group=%d total_ssovfs=%d", res->domain,
- res->vfid, sdev.total_ssovfs);
- return 0;
-}
-
-static const struct rte_pci_id pci_ssovf_map[] = {
- {
- RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
- PCI_DEVICE_ID_OCTEONTX_SSOGRP_VF)
- },
- {
- .vendor_id = 0,
- },
-};
-
-static struct rte_pci_driver pci_ssovf = {
- .id_table = pci_ssovf_map,
- .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
- .probe = ssovf_probe,
-};
-
-RTE_PMD_REGISTER_PCI(octeontx_ssovf, pci_ssovf);
DPDK_17.11 {
- global:
-
- octeontx_ssovf_info;
- octeontx_ssovf_bar;
- octeontx_ssovf_mbox_send;
-
local: *;
};
LIB = librte_pmd_octeontx.a
CFLAGS += $(WERROR_FLAGS)
+CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx/
CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx/
EXPORT_MAP := rte_pmd_octeontx_version.map
CFLAGS_octeontx_ethdev.o += -DALLOW_EXPERIMENTAL_API
LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
-LDLIBS += -lrte_ethdev -lrte_net -lrte_kvargs
+LDLIBS += -lrte_ethdev -lrte_net -lrte_kvargs -lrte_common_octeontx
LDLIBS += -lrte_mempool_octeontx
LDLIBS += -lrte_eventdev
LDLIBS += -lrte_bus_pci
hdr.msg = MBOX_BGX_PORT_OPEN;
hdr.vfid = port;
- res = octeontx_ssovf_mbox_send(&hdr, NULL, 0, &bgx_conf, len);
+ res = octeontx_mbox_send(&hdr, NULL, 0, &bgx_conf, len);
if (res < 0)
return -EACCES;
hdr.msg = MBOX_BGX_PORT_CLOSE;
hdr.vfid = port;
- res = octeontx_ssovf_mbox_send(&hdr, NULL, 0, NULL, 0);
+ res = octeontx_mbox_send(&hdr, NULL, 0, NULL, 0);
if (res < 0)
return -EACCES;
hdr.msg = MBOX_BGX_PORT_START;
hdr.vfid = port;
- res = octeontx_ssovf_mbox_send(&hdr, NULL, 0, NULL, 0);
+ res = octeontx_mbox_send(&hdr, NULL, 0, NULL, 0);
if (res < 0)
return -EACCES;
hdr.msg = MBOX_BGX_PORT_STOP;
hdr.vfid = port;
- res = octeontx_ssovf_mbox_send(&hdr, NULL, 0, NULL, 0);
+ res = octeontx_mbox_send(&hdr, NULL, 0, NULL, 0);
if (res < 0)
return -EACCES;
hdr.vfid = port;
memset(&bgx_conf, 0, sizeof(octeontx_mbox_bgx_port_conf_t));
- res = octeontx_ssovf_mbox_send(&hdr, NULL, 0, &bgx_conf, len);
+ res = octeontx_mbox_send(&hdr, NULL, 0, &bgx_conf, len);
if (res < 0)
return -EACCES;
hdr.msg = MBOX_BGX_PORT_GET_STATUS;
hdr.vfid = port;
- res = octeontx_ssovf_mbox_send(&hdr, NULL, 0, &bgx_stat, len);
+ res = octeontx_mbox_send(&hdr, NULL, 0, &bgx_stat, len);
if (res < 0)
return -EACCES;
hdr.msg = MBOX_BGX_PORT_GET_STATS;
hdr.vfid = port;
- res = octeontx_ssovf_mbox_send(&hdr, NULL, 0, &bgx_stats, len);
+ res = octeontx_mbox_send(&hdr, NULL, 0, &bgx_stats, len);
if (res < 0)
return -EACCES;
hdr.msg = MBOX_BGX_PORT_CLR_STATS;
hdr.vfid = port;
- res = octeontx_ssovf_mbox_send(&hdr, NULL, 0, NULL, 0);
+ res = octeontx_mbox_send(&hdr, NULL, 0, NULL, 0);
if (res < 0)
return -EACCES;
hdr.msg = MBOX_BGX_PORT_GET_LINK_STATUS;
hdr.vfid = port;
- res = octeontx_ssovf_mbox_send(&hdr, NULL, 0, &link, len);
+ res = octeontx_mbox_send(&hdr, NULL, 0, &link, len);
if (res < 0)
return -EACCES;
hdr.vfid = port;
prom = en ? 1 : 0;
- res = octeontx_ssovf_mbox_send(&hdr, &prom, sizeof(prom), NULL, 0);
+ res = octeontx_mbox_send(&hdr, &prom, sizeof(prom), NULL, 0);
if (res < 0)
return -EACCES;
hdr.msg = MBOX_BGX_PORT_SET_MACADDR;
hdr.vfid = port;
- res = octeontx_ssovf_mbox_send(&hdr, mac_addr, len, NULL, 0);
+ res = octeontx_mbox_send(&hdr, mac_addr, len, NULL, 0);
if (res < 0)
return -EACCES;
hdr.msg = MBOX_PKI_PORT_OPEN;
hdr.vfid = port;
- res = octeontx_ssovf_mbox_send(&hdr, NULL, 0, NULL, 0);
+ res = octeontx_mbox_send(&hdr, NULL, 0, NULL, 0);
if (res < 0)
return -EACCES;
return res;
hdr.msg = MBOX_PKI_PORT_HASH_CONFIG;
hdr.vfid = port;
- res = octeontx_ssovf_mbox_send(&hdr, &h_cfg, len, NULL, 0);
+ res = octeontx_mbox_send(&hdr, &h_cfg, len, NULL, 0);
if (res < 0)
return -EACCES;
hdr.msg = MBOX_PKI_PORT_PKTBUF_CONFIG;
hdr.vfid = port;
- res = octeontx_ssovf_mbox_send(&hdr, &b_cfg, len, NULL, 0);
+ res = octeontx_mbox_send(&hdr, &b_cfg, len, NULL, 0);
if (res < 0)
return -EACCES;
return res;
hdr.msg = MBOX_PKI_PORT_CREATE_QOS;
hdr.vfid = port;
- res = octeontx_ssovf_mbox_send(&hdr, &q_cfg, len, NULL, 0);
+ res = octeontx_mbox_send(&hdr, &q_cfg, len, NULL, 0);
if (res < 0)
return -EACCES;
hdr.msg = MBOX_PKI_PORT_ERRCHK_CONFIG;
hdr.vfid = port;
- res = octeontx_ssovf_mbox_send(&hdr, &e_cfg, len, NULL, 0);
+ res = octeontx_mbox_send(&hdr, &e_cfg, len, NULL, 0);
if (res < 0)
return -EACCES;
hdr.msg = MBOX_PKI_PORT_MODIFY_QOS;
hdr.vfid = port;
- res = octeontx_ssovf_mbox_send(&hdr, &q_cfg, len, NULL, 0);
+ res = octeontx_mbox_send(&hdr, &q_cfg, len, NULL, 0);
if (res < 0)
return -EACCES;
hdr.msg = MBOX_PKI_PORT_DELETE_QOS;
hdr.vfid = port;
- res = octeontx_ssovf_mbox_send(&hdr, &q_cfg, len, NULL, 0);
+ res = octeontx_mbox_send(&hdr, &q_cfg, len, NULL, 0);
if (res < 0)
return -EACCES;
hdr.msg = MBOX_PKI_PORT_CLOSE;
hdr.vfid = port;
- res = octeontx_ssovf_mbox_send(&hdr, &ptype, len, NULL, 0);
+ res = octeontx_mbox_send(&hdr, &ptype, len, NULL, 0);
if (res < 0)
return -EACCES;
hdr.msg = MBOX_PKI_PORT_START;
hdr.vfid = port;
- res = octeontx_ssovf_mbox_send(&hdr, &ptype, len, NULL, 0);
+ res = octeontx_mbox_send(&hdr, &ptype, len, NULL, 0);
if (res < 0)
return -EACCES;
hdr.msg = MBOX_PKI_PORT_STOP;
hdr.vfid = port;
- res = octeontx_ssovf_mbox_send(&hdr, &ptype, len, NULL, 0);
+ res = octeontx_mbox_send(&hdr, &ptype, len, NULL, 0);
if (res < 0)
return -EACCES;
_LDLIBS-$(CONFIG_RTE_LIBRTE_KNI) += -lrte_kni
endif
+ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOOL),yy)
+_LDLIBS-y += -lrte_common_octeontx
+endif
+
_LDLIBS-$(CONFIG_RTE_LIBRTE_PCI_BUS) += -lrte_bus_pci
_LDLIBS-$(CONFIG_RTE_LIBRTE_VDEV_BUS) += -lrte_bus_vdev
_LDLIBS-$(CONFIG_RTE_LIBRTE_DPAA_BUS) += -lrte_bus_dpaa
git.droids-corp.org / dpdk.git / commitdiff