net/ixgbe/base: add typecast for type mismatch
authorGuinan Sun <guinanx.sun@intel.com>
Thu, 9 Jul 2020 08:00:37 +0000 (08:00 +0000)
committerFerruh Yigit <ferruh.yigit@intel.com>
Sat, 11 Jul 2020 04:18:53 +0000 (06:18 +0200)
Add typecast for type mismatch.

Signed-off-by: Jakub Chylkowski <jakubx.chylkowski@intel.com>
Signed-off-by: Guinan Sun <guinanx.sun@intel.com>
Reviewed-by: Wei Zhao <wei.zhao1@intel.com>
drivers/net/ixgbe/base/ixgbe_82599.c
drivers/net/ixgbe/base/ixgbe_common.c
drivers/net/ixgbe/base/ixgbe_dcb_82598.c
drivers/net/ixgbe/base/ixgbe_dcb_82599.c
drivers/net/ixgbe/base/ixgbe_x550.c

index 1932337..38ab58d 100644 (file)
@@ -1547,7 +1547,7 @@ void ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
         * is for FDIRCMD.  Then do a 64-bit register write from FDIRHASH.
         */
        fdirhashcmd = (u64)fdircmd << 32;
-       fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
+       fdirhashcmd |= (u64)ixgbe_atr_compute_sig_hash_82599(input, common);
        IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
 
        DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
@@ -1636,7 +1636,7 @@ STATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
 {
        u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
        mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
-       mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
+       mask |= (u32)IXGBE_NTOHS(input_mask->formatted.src_port);
        mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
        mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
        mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
@@ -1868,14 +1868,14 @@ s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
                /* record source and destination port (little-endian)*/
                fdirport = IXGBE_NTOHS(input->formatted.dst_port);
                fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
-               fdirport |= IXGBE_NTOHS(input->formatted.src_port);
+               fdirport |= (u32)IXGBE_NTOHS(input->formatted.src_port);
                IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
        }
 
        /* record VLAN (little-endian) and flex_bytes(big-endian) */
        fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
        fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
-       fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
+       fdirvlan |= (u32)IXGBE_NTOHS(input->formatted.vlan_id);
        IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
 
        if (cloud_mode) {
index d98d5a9..cecc647 100644 (file)
@@ -738,7 +738,7 @@ s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
                DEBUGOUT("NVM Read Error\n");
                return ret_val;
        }
-       *pba_num |= data;
+       *pba_num |= (u32)data;
 
        return IXGBE_SUCCESS;
 }
index dc7b905..b17c02c 100644 (file)
@@ -159,7 +159,7 @@ s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
        for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
                max_credits = max[i];
                reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
-               reg |= refill[i];
+               reg |= (u32)(refill[i]);
                reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
 
                if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
index 04e0d1f..c26aaab 100644 (file)
@@ -166,7 +166,7 @@ s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
        for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
                max_credits = max[i];
                reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;
-               reg |= refill[i];
+               reg |= (u32)(refill[i]);
                reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;
 
                if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
index 5750f79..d3363ff 100644 (file)
@@ -699,7 +699,7 @@ static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
 
        for (i = 0; i < sizeof(ixgbe_fw_map) / sizeof(ixgbe_fw_map[0]); ++i) {
                if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
-                       setup[0] |= ixgbe_fw_map[i].fw_speed;
+                       setup[0] |= (u32)(ixgbe_fw_map[i].fw_speed);
        }
        setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;