crypto/qat: add aes-sha384-hmac capability

Enable support of aes-sha384-hmac in Intel(R) QuickAssist driver.

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 7f630be..78a734f 100644 (file)
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -55,6 +55,7 @@ Hash algorithms:
 * ``RTE_CRYPTO_AUTH_SHA1_HMAC``
 * ``RTE_CRYPTO_AUTH_SHA224_HMAC``
 * ``RTE_CRYPTO_AUTH_SHA256_HMAC``
+* ``RTE_CRYPTO_AUTH_SHA384_HMAC``
 * ``RTE_CRYPTO_AUTH_SHA512_HMAC``
 * ``RTE_CRYPTO_AUTH_AES_XCBC_MAC``
 * ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``

diff --git a/doc/guides/rel_notes/release_16_11.rst b/doc/guides/rel_notes/release_16_11.rst
index 858bfe8..cfa3748 100644 (file)
--- a/doc/guides/rel_notes/release_16_11.rst
+++ b/doc/guides/rel_notes/release_16_11.rst
@@ -70,6 +70,7 @@ New Features
 
   * MD5_HMAC algorithm
   * SHA224-HMAC algorithm
+  * SHA384-HMAC algorithm
 
 
 Resolved Issues

diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index d8c4329..4bdd7eb 100644 (file)
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -77,6 +77,9 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo qat_hash_alg)
        case ICP_QAT_HW_AUTH_ALGO_SHA256:
                return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA256_STATE1_SZ,
                                                QAT_HW_DEFAULT_ALIGNMENT);
+       case ICP_QAT_HW_AUTH_ALGO_SHA384:
+               return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA384_STATE1_SZ,
+                                               QAT_HW_DEFAULT_ALIGNMENT);
        case ICP_QAT_HW_AUTH_ALGO_SHA512:
                return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ,
                                                QAT_HW_DEFAULT_ALIGNMENT);
@@ -114,6 +117,8 @@ static int qat_hash_get_digest_size(enum icp_qat_hw_auth_algo qat_hash_alg)
                return ICP_QAT_HW_SHA224_STATE1_SZ;
        case ICP_QAT_HW_AUTH_ALGO_SHA256:
                return ICP_QAT_HW_SHA256_STATE1_SZ;
+       case ICP_QAT_HW_AUTH_ALGO_SHA384:
+               return ICP_QAT_HW_SHA384_STATE1_SZ;
        case ICP_QAT_HW_AUTH_ALGO_SHA512:
                return ICP_QAT_HW_SHA512_STATE1_SZ;
        case ICP_QAT_HW_AUTH_ALGO_MD5:
@@ -138,6 +143,8 @@ static int qat_hash_get_block_size(enum icp_qat_hw_auth_algo qat_hash_alg)
                return SHA256_CBLOCK;
        case ICP_QAT_HW_AUTH_ALGO_SHA256:
                return SHA256_CBLOCK;
+       case ICP_QAT_HW_AUTH_ALGO_SHA384:
+               return SHA512_CBLOCK;
        case ICP_QAT_HW_AUTH_ALGO_SHA512:
                return SHA512_CBLOCK;
        case ICP_QAT_HW_AUTH_ALGO_GALOIS_128:
@@ -187,6 +194,17 @@ static int partial_hash_sha256(uint8_t *data_in, uint8_t *data_out)
        return 0;
 }
 
+static int partial_hash_sha384(uint8_t *data_in, uint8_t *data_out)
+{
+       SHA512_CTX ctx;
+
+       if (!SHA384_Init(&ctx))
+               return -EFAULT;
+       SHA512_Transform(&ctx, data_in);
+       rte_memcpy(data_out, &ctx, SHA512_DIGEST_LENGTH);
+       return 0;
+}
+
 static int partial_hash_sha512(uint8_t *data_in, uint8_t *data_out)
 {
        SHA512_CTX ctx;
@@ -251,6 +269,13 @@ static int partial_hash_compute(enum icp_qat_hw_auth_algo hash_alg,
                        *hash_state_out_be32 =
                                rte_bswap32(*(((uint32_t *)digest)+i));
                break;
+       case ICP_QAT_HW_AUTH_ALGO_SHA384:
+               if (partial_hash_sha384(data_in, digest))
+                       return -EFAULT;
+               for (i = 0; i < digest_size >> 3; i++, hash_state_out_be64++)
+                       *hash_state_out_be64 =
+                               rte_bswap64(*(((uint64_t *)digest)+i));
+               break;
        case ICP_QAT_HW_AUTH_ALGO_SHA512:
                if (partial_hash_sha512(data_in, digest))
                        return -EFAULT;
@@ -615,6 +640,14 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,
                }
                state2_size = ICP_QAT_HW_SHA256_STATE2_SZ;
                break;
+       case ICP_QAT_HW_AUTH_ALGO_SHA384:
+               if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA384,
+                       authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+                       PMD_DRV_LOG(ERR, "(SHA)precompute failed");
+                       return -EFAULT;
+               }
+               state2_size = ICP_QAT_HW_SHA384_STATE2_SZ;
+               break;
        case ICP_QAT_HW_AUTH_ALGO_SHA512:
                if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA512,
                        authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {

diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index f4088dd..661ebb2 100644 (file)
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -131,6 +131,27 @@ static const struct rte_cryptodev_capabilities qat_pmd_capabilities[] = {
                        }, }
                }, }
        },
+       {       /* SHA384 HMAC */
+               .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+               {.sym = {
+                       .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+                       {.auth = {
+                               .algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
+                               .block_size = 64,
+                               .key_size = {
+                                       .min = 128,
+                                       .max = 128,
+                                       .increment = 0
+                               },
+                               .digest_size = {
+                                       .min = 48,
+                                       .max = 48,
+                                       .increment = 0
+                                       },
+                               .aad_size = { 0 }
+                       }, }
+               }, }
+       },
        {       /* SHA512 HMAC */
                .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
                {.sym = {
@@ -553,15 +574,18 @@ qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
        case RTE_CRYPTO_AUTH_SHA1_HMAC:
                session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
                break;
+       case RTE_CRYPTO_AUTH_SHA224_HMAC:
+               session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
+               break;
        case RTE_CRYPTO_AUTH_SHA256_HMAC:
                session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
                break;
+       case RTE_CRYPTO_AUTH_SHA384_HMAC:
+               session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
+               break;
        case RTE_CRYPTO_AUTH_SHA512_HMAC:
                session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
                break;
-       case RTE_CRYPTO_AUTH_SHA224_HMAC:
-               session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
-               break;
        case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
                session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
                break;
@@ -580,7 +604,6 @@ qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
        case RTE_CRYPTO_AUTH_SHA512:
        case RTE_CRYPTO_AUTH_SHA224:
        case RTE_CRYPTO_AUTH_SHA384:
-       case RTE_CRYPTO_AUTH_SHA384_HMAC:
        case RTE_CRYPTO_AUTH_MD5:
        case RTE_CRYPTO_AUTH_AES_CCM:
        case RTE_CRYPTO_AUTH_AES_GMAC: