net/cxgbe: set default PCIe completion timeout

Program the PCIe completion timeout to 4 sec to give enough time
to allow completions to be received successfully in some older systems.

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>

diff --git a/drivers/net/cxgbe/base/adapter.h b/drivers/net/cxgbe/base/adapter.h
index af347214548ffec7621f49e88d9a49653d2d4690..73e7aca6cd0e675781b539f56e5a25148a7e4b32 100644 (file)
--- a/drivers/net/cxgbe/base/adapter.h
+++ b/drivers/net/cxgbe/base/adapter.h
@@ -431,8 +431,10 @@ static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr,
 #define PCI_STATUS_CAP_LIST     0x10    /* Support Capability List */
 #define PCI_CAPABILITY_LIST     0x34
 /* Offset of first capability list entry */
+#define PCI_CAP_ID_EXP          0x10    /* PCI Express */
 #define PCI_CAP_LIST_ID         0       /* Capability ID */
 #define PCI_CAP_LIST_NEXT       1       /* Next capability in the list */
+#define PCI_EXP_DEVCTL2         40      /* Device Control 2 */
 
 /**
  * t4_os_pci_write_cfg4 - 32-bit write to PCI config space

diff --git a/drivers/net/cxgbe/base/t4_hw.c b/drivers/net/cxgbe/base/t4_hw.c
index 79af806744a8b9266a5ba307393a1f8ac0aaad63..7882f9af57fcf4492d893782ef207cfd384cc571 100644 (file)
--- a/drivers/net/cxgbe/base/t4_hw.c
+++ b/drivers/net/cxgbe/base/t4_hw.c
@@ -1,7 +1,7 @@
 /*-
  *   BSD LICENSE
  *
- *   Copyright(c) 2014-2015 Chelsio Communications.
+ *   Copyright(c) 2014-2016 Chelsio Communications.
  *   All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
@@ -2326,6 +2326,21 @@ int t4_get_flash_params(struct adapter *adapter)
        return 0;
 }
 
+static void set_pcie_completion_timeout(struct adapter *adapter,
+                                       u8 range)
+{
+       u32 pcie_cap;
+       u16 val;
+
+       pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
+       if (pcie_cap) {
+               t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
+               val &= 0xfff0;
+               val |= range;
+               t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
+       }
+}
+
 /**
  * t4_prep_adapter - prepare SW and HW for operation
  * @adapter: the adapter
@@ -2384,6 +2399,8 @@ int t4_prep_adapter(struct adapter *adapter)
        adapter->params.portvec = 1;
        adapter->params.vpd.cclk = 50000;
 
+       /* Set pci completion timeout value to 4 seconds. */
+       set_pcie_completion_timeout(adapter, 0xd);
        return 0;
 }