ixgbe/base: flow director changes
authorJijiang Liu <jijiang.liu@intel.com>
Wed, 18 Jun 2014 19:52:48 +0000 (21:52 +0200)
committerThomas Monjalon <thomas.monjalon@6wind.com>
Wed, 18 Jun 2014 21:31:59 +0000 (23:31 +0200)
Signed-off-by: Jijiang Liu <jijiang.liu@intel.com>
Acked-by: Helin Zhang <helin.zhang@intel.com>
Tested-by: Waterman Cao <waterman.cao@intel.com>
[Thomas: split code drop]

lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c
lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h
lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
lib/librte_pmd_ixgbe/ixgbe_fdir.c

index 13fa4da..8bc5320 100644 (file)
@@ -1464,8 +1464,10 @@ s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
  *  @hw: pointer to hardware structure
  *  @fdirctrl: value to write to flow director control register, initially
  *          contains just the value of the Rx packet buffer allocation
+ *  @cloud_mode: true - cloude mode, false - other mode
  **/
-s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
+s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
+                       bool cloud_mode)
 {
        DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
 
@@ -1662,34 +1664,20 @@ void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
 
        u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
        u32 bucket_hash = 0;
+       u32 hi_dword = 0;
+       u32 i = 0;
 
        /* Apply masks to input data */
-       input->dword_stream[0]  &= input_mask->dword_stream[0];
-       input->dword_stream[1]  &= input_mask->dword_stream[1];
-       input->dword_stream[2]  &= input_mask->dword_stream[2];
-       input->dword_stream[3]  &= input_mask->dword_stream[3];
-       input->dword_stream[4]  &= input_mask->dword_stream[4];
-       input->dword_stream[5]  &= input_mask->dword_stream[5];
-       input->dword_stream[6]  &= input_mask->dword_stream[6];
-       input->dword_stream[7]  &= input_mask->dword_stream[7];
-       input->dword_stream[8]  &= input_mask->dword_stream[8];
-       input->dword_stream[9]  &= input_mask->dword_stream[9];
-       input->dword_stream[10] &= input_mask->dword_stream[10];
+       for (i = 0; i < 14; i++)
+               input->dword_stream[i]  &= input_mask->dword_stream[i];
 
        /* record the flow_vm_vlan bits as they are a key part to the hash */
        flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
 
        /* generate common hash dword */
-       hi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^
-                                   input->dword_stream[2] ^
-                                   input->dword_stream[3] ^
-                                   input->dword_stream[4] ^
-                                   input->dword_stream[5] ^
-                                   input->dword_stream[6] ^
-                                   input->dword_stream[7] ^
-                                   input->dword_stream[8] ^
-                                   input->dword_stream[9] ^
-                                   input->dword_stream[10]);
+       for (i = 1; i <= 13; i++)
+               hi_dword ^= input->dword_stream[i];
+       hi_hash_dword = IXGBE_NTOHL(hi_dword);
 
        /* low dword is word swapped version of common */
        lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
@@ -1708,21 +1696,8 @@ void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
        lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
 
        /* Process remaining 30 bit of the key */
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
-       IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
+       for (i = 1; i <= 15; i++)
+               IXGBE_COMPUTE_BKT_HASH_ITERATION(i);
 
        /*
         * Limit hash to 13 bits since max bucket count is 8K.
@@ -1769,7 +1744,7 @@ STATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
        IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
 
 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
-                                   union ixgbe_atr_input *input_mask)
+                                   union ixgbe_atr_input *input_mask, bool cloud_mode)
 {
        /* mask IPv6 since it is currently not supported */
        u32 fdirm = IXGBE_FDIRM_DIPv6;
@@ -1868,7 +1843,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
 
 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
                                          union ixgbe_atr_input *input,
-                                         u16 soft_id, u8 queue)
+                                         u16 soft_id, u8 queue, bool cloud_mode)
 {
        u32 fdirport, fdirvlan, fdirhash, fdircmd;
 
@@ -1917,6 +1892,8 @@ s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
                  IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
        if (queue == IXGBE_FDIR_DROP_QUEUE)
                fdircmd |= IXGBE_FDIRCMD_DROP;
+       if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK)
+               fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
        fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
        fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
        fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
@@ -1983,7 +1960,7 @@ s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
                                        union ixgbe_atr_input *input,
                                        union ixgbe_atr_input *input_mask,
-                                       u16 soft_id, u8 queue)
+                                       u16 soft_id, u8 queue, bool cloud_mode)
 {
        s32 err = IXGBE_ERR_CONFIG;
 
@@ -1995,6 +1972,7 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
         */
        switch (input->formatted.flow_type) {
        case IXGBE_ATR_FLOW_TYPE_IPV4:
+       case IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4:
                input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
                if (input->formatted.dst_port || input->formatted.src_port) {
                        DEBUGOUT(" Error on src/dst port\n");
@@ -2002,12 +1980,15 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
                }
                break;
        case IXGBE_ATR_FLOW_TYPE_SCTPV4:
+       case IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4:
                if (input->formatted.dst_port || input->formatted.src_port) {
                        DEBUGOUT(" Error on src/dst port\n");
                        return IXGBE_ERR_CONFIG;
                }
        case IXGBE_ATR_FLOW_TYPE_TCPV4:
+       case IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4:
        case IXGBE_ATR_FLOW_TYPE_UDPV4:
+       case IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4:
                input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
                                                  IXGBE_ATR_L4TYPE_MASK;
                break;
@@ -2017,7 +1998,7 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
        }
 
        /* program input mask into the HW */
-       err = ixgbe_fdir_set_input_mask_82599(hw, input_mask);
+       err = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode);
        if (err)
                return err;
 
@@ -2026,7 +2007,7 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
 
        /* program filters to filter memory */
        return ixgbe_fdir_write_perfect_filter_82599(hw, input,
-                                                    soft_id, queue);
+                                                    soft_id, queue, cloud_mode);
 }
 
 /**
index 4e20213..47e4f6d 100644 (file)
@@ -139,16 +139,17 @@ s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw);
 s32 ixgbe_mng_fw_enabled(struct ixgbe_hw *hw);
 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
-s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
+s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
+                                       bool cloud_mode);
 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
                                          union ixgbe_atr_hash_dword input,
                                          union ixgbe_atr_hash_dword common,
                                          u8 queue);
 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
-                                   union ixgbe_atr_input *input_mask);
+                                   union ixgbe_atr_input *input_mask, bool cloud_mode);
 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
                                          union ixgbe_atr_input *input,
-                                         u16 soft_id, u8 queue);
+                                         u16 soft_id, u8 queue, bool cloud_mode);
 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
                                          union ixgbe_atr_input *input,
                                          u16 soft_id);
@@ -156,7 +157,8 @@ s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
                                        union ixgbe_atr_input *input,
                                        union ixgbe_atr_input *mask,
                                        u16 soft_id,
-                                       u8 queue);
+                                       u8 queue,
+                                       bool cloud_mode);
 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
                                          union ixgbe_atr_input *mask);
 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
index 1d3b60a..7dd2fdf 100644 (file)
@@ -332,6 +332,7 @@ POSSIBILITY OF SUCH DAMAGE.
 #define IXGBE_FDIRSIP4M        0x0EE40
 #define IXGBE_FDIRTCPM 0x0EE44
 #define IXGBE_FDIRUDPM 0x0EE48
+#define IXGBE_FDIRSCTPM        0x0EE78
 #define IXGBE_FDIRIP6M 0x0EE74
 #define IXGBE_FDIRM    0x0EE70
 
@@ -2340,6 +2341,7 @@ enum ixgbe_fdir_pballoc_type {
 #define IXGBE_FDIRCTRL_DROP_Q_SHIFT            8
 #define IXGBE_FDIRCTRL_FLEX_SHIFT              16
 #define IXGBE_FDIRCTRL_SEARCHLIM               0x00800000
+#define IXGBE_FDIRCTRL_FILTERMODE_MASK         0x00E00000
 #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT                24
 #define IXGBE_FDIRCTRL_FULL_THRESH_MASK                0xF0000000
 #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT       28
@@ -2394,10 +2396,11 @@ enum ixgbe_fdir_pballoc_type {
 #define IXGBE_FDIRCMD_QUEUE_EN                 0x00008000
 #define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT          5
 #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT           16
+#define IXGBE_FDIRCMD_TUNNEL_FILTER_SHIFT      23
 #define IXGBE_FDIRCMD_VT_POOL_SHIFT            24
 #define IXGBE_FDIR_INIT_DONE_POLL              10
 #define IXGBE_FDIRCMD_CMD_POLL                 10
-
+#define IXGBE_FDIRCMD_TUNNEL_FILTER            0x00800000
 #define IXGBE_FDIR_DROP_QUEUE                  127
 
 #define IXGBE_STATUS_OVERHEATING_BIT           20 /* STATUS overtemp bit num */
@@ -2686,6 +2689,7 @@ typedef u32 ixgbe_physical_layer;
 #define IXGBE_ATR_L4TYPE_TCP           0x2
 #define IXGBE_ATR_L4TYPE_SCTP          0x3
 #define IXGBE_ATR_L4TYPE_IPV6_MASK     0x4
+#define IXGBE_ATR_L4TYPE_TUNNEL_MASK   0x10
 enum ixgbe_atr_flow_type {
        IXGBE_ATR_FLOW_TYPE_IPV4        = 0x0,
        IXGBE_ATR_FLOW_TYPE_UDPV4       = 0x1,
@@ -2695,6 +2699,14 @@ enum ixgbe_atr_flow_type {
        IXGBE_ATR_FLOW_TYPE_UDPV6       = 0x5,
        IXGBE_ATR_FLOW_TYPE_TCPV6       = 0x6,
        IXGBE_ATR_FLOW_TYPE_SCTPV6      = 0x7,
+       IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4       = 0x10,
+       IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4      = 0x11,
+       IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4      = 0x12,
+       IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4     = 0x13,
+       IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV6       = 0x14,
+       IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV6      = 0x15,
+       IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV6      = 0x16,
+       IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV6     = 0x17,
 };
 
 /* Flow Director ATR input struct. */
@@ -2706,6 +2718,9 @@ union ixgbe_atr_input {
         * flow_type    - 1 byte
         * vlan_id      - 2 bytes
         * src_ip       - 16 bytes
+        * inner_mac    - 6 bytes
+        * cloud_mode   - 2 bytes
+        * tni_vni      - 4 bytes
         * dst_ip       - 16 bytes
         * src_port     - 2 bytes
         * dst_port     - 2 bytes
@@ -2718,12 +2733,15 @@ union ixgbe_atr_input {
                __be16 vlan_id;
                __be32 dst_ip[4];
                __be32 src_ip[4];
+               u8 inner_mac[6];
+               __be16 tunnel_type;
+               __be32 tni_vni;
                __be16 src_port;
                __be16 dst_port;
                __be16 flex_bytes;
                __be16 bkt_hash;
        } formatted;
-       __be32 dword_stream[11];
+       __be32 dword_stream[14];
 };
 
 /* Flow Director compressed ATR hash input struct */
index bf9fe69..6c0a530 100644 (file)
@@ -280,9 +280,8 @@ ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
        flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]);
 
        /* generate common hash dword */
-       for (i = 10; i; i -= 2)
-               common_hash_dword ^= atr_input->dword_stream[i] ^
-                                    atr_input->dword_stream[i - 1];
+       for (i = 1; i <= 13; i++)
+               common_hash_dword ^= atr_input->dword_stream[i];
 
        hi_hash_dword = IXGBE_NTOHL(common_hash_dword);