net/mlx5: support checksum offload on Windows

Support of the checksum offloading by checking
the relevant FW capability (csum_cap) for NIC support.

RX supported offloads:

DEV_RX_OFFLOAD_IPV4_CKSUM
DEV_RX_OFFLOAD_UDP_CKSUM
DEV_RX_OFFLOAD_TCP_CKSUM

TX supported offloads:

DEV_TX_OFFLOAD_IPV4_CKSUM
DEV_TX_OFFLOAD_UDP_CKSUM
DEV_TX_OFFLOAD_TCP_CKSUM

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Tested-by: Odi Assli <odia@nvidia.com>

diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c
index 5e53042..3fe3f55 100644 (file)
--- a/drivers/net/mlx5/windows/mlx5_os.c
+++ b/drivers/net/mlx5/windows/mlx5_os.c
@@ -420,8 +420,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
        err = mlx5_dev_check_sibling_config(priv, config);
        if (err)
                goto error;
-       DRV_LOG(DEBUG, "checksum offloading is %ssupported",
-               (config->hw_csum ? "" : "not "));
        DRV_LOG(DEBUG, "counters are not supported");
        config->ind_table_max_size =
                sh->device_attr.max_rwq_indirection_table_size;
@@ -464,6 +462,9 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
                        sh->cmng.relaxed_ordering_read =
                                config->hca_attr.relaxed_ordering_read;
                }
+               config->hw_csum = config->hca_attr.csum_cap;
+               DRV_LOG(DEBUG, "checksum offloading is %ssupported",
+                   (config->hw_csum ? "" : "not "));
        }
        if (config->devx) {
                uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];