net/iavf: fix queue interrupt for ice

Enable CLEARPBA bit is required by ice NIC of A0/A1 version to
enable Tx and Rx queue interrupt.
Also enable CLEARPBA bit does no impact on IAVF behaviour when be
hosted by other devices, so we can make it as default.

Fixes: d6bde6b5eae9 ("net/avf: enable Rx interrupt")
Cc: stable@dpdk.org
Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>

diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c
index 7825cbc85c6ff6dea6dd92ba1d4d4792c6fbc6be..7a0696ed725d9a5c67d665461f8cabe3ac0f59e6 100644 (file)
--- a/drivers/net/iavf/iavf_ethdev.c
+++ b/drivers/net/iavf/iavf_ethdev.c
@@ -1014,11 +1014,13 @@ iavf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
                PMD_DRV_LOG(INFO, "MISC is also enabled for control");
                IAVF_WRITE_REG(hw, IAVFINT_DYN_CTL01,
                              IAVFINT_DYN_CTL01_INTENA_MASK |
+                             IAVFINT_DYN_CTL01_CLEARPBA_MASK |
                              IAVFINT_DYN_CTL01_ITR_INDX_MASK);
        } else {
                IAVF_WRITE_REG(hw,
                              IAVFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START),
                              IAVFINT_DYN_CTLN1_INTENA_MASK |
+                             IAVFINT_DYN_CTL01_CLEARPBA_MASK |
                              IAVFINT_DYN_CTLN1_ITR_INDX_MASK);
        }